An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms
Author Name: Charan Kumar K and Sunil Kumar K
Synopsis:
This paper presents the design and comparison of the high speed single precision binary floating point multiplier using IEEE-754 format implemented through the Faster Dadda, Vedic from Dadda and the modified Booth algorithm. The Faster Dadda algorithm utilizes the parallel independent column compression technique and the Hybrid adder. The Vedic from Dadda is the concept of utilizing the Dadda to get higher order multiplier through Vedic concept. Integer multiplication can be inefficient and costly, in time and hardware, depending on the representation of signed numbers. The modified Booth algorithm uses the encoding techniques which minimize the partial products. These single precision Floating point multipliers based on IEEE 754 are implemented using VHDL and they are targeted for Xilinx Spartan-3E FPGA. The performances of these multipliers are analysed in terms of speed, area and area-delay product.

Design of FIR Filter for Efficient FPGA Implementation

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: Design of FIR Filter for Efficient FPGA Implementation
Author Name: S.V. Padmajarani and M. Muralidhar
Synopsis:
FIR filters are basic building blocks in Digital Signal Processing applications, require computationally efficient multiply and accumulate operations so the blocks with the desired characteristics have to be chosen carefully. The multiplier is generally slow and occupies large area, the adder also contributes to long delay when the length of the addition is more. Improving the speed results mostly in large areas, usually they conflict with each other. The signal processing applications consume considerable amount of energy. Hence there is a need for low power, high speed, low area circuits for Digital Signal Processing applications. The aim of this paper is to implement a low power, high speed, area efficient FIR filter. Multiply and Accumulate technique is used for multiplier design and the addition and accumulation operations are performed by Parallel Prefix Adders. Some of the available Parallel Prefix Adder architectures and the hybrid architecture of Parallel prefix adder is used here. The implementation is done for 4-tap FIR filter using Xilinx 14.5 version, with the targeted device of Spartan3E FPGA. The experimental results show that the implemented FIR filter using hybrid parallel prefix adder is efficient in area, consume low power and has high speed compared to existing parallel prefix adder models.

Memory Implementation using Multi Bit Flip-Flop

Vol. 5  Issue 2
Year: 2015
Issue: Dec-Feb
Title: Memory Implementation using Multi Bit Flip-Flop
Author Name: Palagani Yellappa, Mareddi Bharathkumar and Shaik Shabana Azmi
Synopsis:
In the digital world memory elements play a vital role. In memory devices the most important factors are Area, Power and Speed. Increased Area and Power consumption of the memory device means reduced device reliability and lifetime. Flip-flops are the basic sequential components used for memory applications. D Flip-flop is one of the most commonly used Flip-flops and delay consumed by clocking is a major part of the whole design. In this paper, the authors analyze the design of Single-Bit Flip-Flop (SBFF i.e. 1-bit) and make a performance comparison over the Multi-Bit Flip-Flop (MBFF i.e. 2-bit, 4-bit, 8-bit, 16-bit and 32-bit). In this paper, the authors design SRAM and DRAM using both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). Designing the memory by using SBFF implies more power consumption. To get the maximum reduction in power and delay an algorithm has been proposed in which SBFFs are replaced with maximum possible MBFF without affecting the performance of the original circuit. These result in favor of Multi-Bit Flip-Flop as reduction of delay such as gate delay and net delay.

VLSI Modeling Of FM0/Manchester Encoder Using EDML Technique For DSRC Application Systems

Vol. 5  Issue 2
Year: 2015
Issue: Dec-Feb
Title: VLSI Modeling Of FM0/Manchester Encoder Using EDML Technique For DSRC Application Systems
Author Name: P. Lokesh, V. Thrimurthulu and L. Mihira Priya
Synopsis:
The aim of this paper is to promote intelligent road and vehicle safety systems in order to control the accident rates and vehicle damages by using Dedicated Short Range Communication (DSRC). The DSRC is of two types: automobile-toautomobile and automobile-to-roadside. In automobile-to-automobile, the DSRC has the ability of message sending and broadcasting among automobiles for safety issues and public information announcement. In this paper, the authors propose a complete simulation model of Dual Mode Logic, (DML) Technique. This method increases the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings being used for the Dedicated Short- Range Communication (DSRC) which is a budding technique to drive the smart transportation system into our daily life with low power digital system designs. The maximum operating frequency is 7GHz and 4GHz for Manchester and FM0 encoding. The on board power consumption is 1133 mW at 3.352 V for Manchester encoding and 1106 mW at 3.352 V for FM0 encoding. The presentation of this paper is evaluates 32nm CMOS technology by utilizing the design simulation Xilinx Vivado tools and layout simulation with extended DML Techniques using Microwind simulator. This paper not only provides a fully reused architecture but also exhibits high performance.

Bridgeless PFC Implementation Using One Cycle Control Technique

Vol. 5  Issue 2
Year: 2015
Issue: Dec-Feb
Title: Bridgeless PFC Implementation Using One Cycle Control Technique
Author Name: K. Prathibha and M. Vasudeva Reddy
Synopsis:
To reduce the rectifier bridge conduction loss, different topologies have been developed. Among these topologies, the bridgeless boost does not require range switch and shows both simplicity and high performance. Without the input rectifier bridge, bridgeless PFC generates less conduction loss as compared to the conventional PFC. Although the circuit structure is simple, the location of the boost inductor on the AC side makes it difficult to sense the AC line voltage and inductor current. At the same time, since the AC side inductor structure makes the output floating regarding the input line, the circuit suffers from high common mode noise. Compared to the average current mode control, one cycle control shows many benefits such as no multiplier requirement, no input voltage sensing requirement, and no inductor current sensing requirement. Therefore, one cycle control gives an attractive solution for the bridgeless PFC circuit. In this paper, One Cycle Control technique is implemented in the bridgeless PFC. By using one cycle control both the voltage sensing and current sensing issues of the bridgeless PFC circuit can be solved. The experimental results show both efficiency improvement and good power factor correction function. At the same time EMI results show that the circuit noise is controllable.

Design and Simulation of RF-MEMS Integrated Reconfigurable Antenna for Wideband Applications

Vol. 5  Issue 2
Year: 2015
Issue: Dec-Feb
Title: Design and Simulation of RF-MEMS Integrated Reconfigurable Antenna for Wideband Applications
Author Name: K. Nalini and V. R. Anitha
Synopsis:
Reconfigurability is the ability to adaptively change the characteristics in an antenna system. In this paper, Radio Frequency-Micro Electro Mechanical Switches (RF-MEMS) are integrated to provide a reconfigurable antenna system that radiates similar patterns over a wide range of frequencies. The different issues encountered during the integration of MEMS switches and the overall system design procedure will be described in this work. The final model will radiate at different frequencies with various radiation patterns. The proposed antenna can be used for the wide band applications in the range of DC to 40 GHz range with reconfigurability.

An SDR Architecture for Linearizing RF Power Amplifier with DPD Technique

Vol. 5  Issue 2
Year: 2015
Issue: Dec-Feb
Title: An SDR Architecture for Linearizing RF Power Amplifier with DPD Technique
Author Name: Asif Ahmed
Synopsis:
In wireless transmission systems, non-ideal response of different functional components along with non linearity of power amplifier plays a major role in degrading the transmitter performance. Several parameters define the performance of a wireless, such as Adjacent Channel Power Ratio (ACPR), Error Vector Magnitude (EVM), spectral mask, etc., and the effect of non-ideal behavior of the transmitter affects these parameters. In many standards, these parameter specifications are defined such that the concern for transmitter linearization is very much relaxed. Standards like Terrestrial Trunked Radio (TETRA) specify strict regulation on these parameters. Therefore, the requirement of linearity is a great challenge for the design of a transmitter, and among these the Digital Pre-distortion (DPD) technique is a wellknown concept. In this paper, an appropriate architecture of SDR is presented for successful operation of the DPD technique. Both signal processing and physical layer architecture may be utilized for complete implementation of the SDR system.