An Electronics Solution to Facilitate Smart City for Waste Management

Volume 9 Issue 3 March - May 2019

Research Paper

An Electronics Solution to Facilitate Smart City for Waste Management

Deepali M. Adat*, Prashant V. Mane Deshmukh**, S. K. Tilekar***, B. P. Lagaonkar****

*,***Shankarrao Mohite College, Akluj, Solapur, India.

**Department of Electronics, Jayawantrao Sawant College of Commerce and Science, Hadapsar, Pune, India.

****Department of Electronics, Shankarrao Mohite College, Akluj, Solapur, India.

Adat, D. M., Deshmukh, P. V. M., Tilekar, S. K., & Lagaonkar, B. P. (2019). An Electronics Solution to Facilitate Smart City for Waste Management. i-manager's Journal on Electronics Engineering, 9(3), 38-44. https://doi.org/10.26634/jele.9.3.15179

Abstract

Recently, Government of India has been implementing the schemes of smart city for various cities. The smart city services such as transportation, security, water distribution, electricity distribution, environmental pollution monitoring, waste management, etc., are the major services, which should be made smart to realize the theme of smart city. Out of these services, waste management plays a commendable role in making the city smart. Collections of waste management of the same are the major problems in many cities. Therefore, the present research work is undertaken for designing of smart electronic solution for waste management. To achieve the desired goal of waste management of smart city, an innovative technology, called popular embedded technology and Wireless Sensor Network (WSN) are used, where embedded technology helps to design the application and user interface layer and the WSN helps to integrate communication layer with application layer. Out of several concepts of Smart City, the authors have selected to facilitate the smart dustbin for smart city. The hardware part of the system is wired about PIC microcontroller and for wireless communication, the IEEE 805.15.4 standard based Zigbee module is strengthened. In addition to this, to monitor the waste, the weight and level sensor is used. The software part is developed in embedded system and after that calibration system is implemented for desired application typically dustbin monitoring. On investigation, the system works with reliability and high accuracy.

UAV: A Novel Approach Towards Armed Conflicts

Volume 9 Issue 3 March - May 2019

Research Paper

UAV: A Novel Approach Towards Armed Conflicts

Chalamaneni Jeevan Prasad*, Uppalapati Somalatha**

*Department of Electronic Communication and Engineering, VEMU Institute of Technology, Andhra Pradesh, India.

**Indian Institute of Technology, Andhra Pradesh, India.

Prasad, C. J., Somalatha, U. (2019). UAV: A Novel Approach Towards Armed Conflicts. i-manager's Journal on Electronics Engineering, 9(3), 32-37. https://doi.org/10.26634/jele.9.3.15181

Abstract

In this paper, the rapidly emerging global landscape, introduction, working, and new implementations of remotely piloted aerial vehicles which will be highly effective for use in defence has been explained. This paper presents a novel way for effective functioning and to reduce the problems encountered by military personnel. This UAV is merely different from that of the existing UAVs. This UAV possesses single propeller connected to a brushless motor present in the middle of the UAV and it has excellent subsystem with a good recovery system, which will be useful in recovering data back. It has the technology that can reproduce its energy (power) back as a boots trapper is connected to the rotor where it will power back. It has different sensors like Ultrasonic Sensor (to detect obstacle), Chemical Sensor (to detect chemicals), Sensing Sensor (to operate UAV), etc. It can not only fly, but also can move on the earth. It can adjust to various o environmental conditions. It has a good battery system (it can work for long time). The camera can rotate in 360 and it will give 3D image processing. It works not only on GPS, but also on sensor. This UAV contains high security to data, if caught by an opponent they cannot read the data. If anyone wants to see data, then the person who is operating or the commander chief's biometric is needed. The UAV has an option of auto pilot (autonomous riding capacity). This research work mainly deals with army personnel as these type of UAVs could save many lives. Finally, the paper identifies a specific comprehensive manner for the future policy in military applications.

Design of High Performance Pulse Generator to Perform Automatic Test in VLSI Circuits

Volume 9 Issue 3 March - May 2019

Research Paper

Design of High Performance Pulse Generator to Perform Automatic Test in VLSI Circuits

P. Lokesh*, V. Thrimurthulu**, L. Mihira Priya***

*_***Department of Electronics and Communication Engineering, Chadalawada Ramanamma Engineering College, Tirupati, India.

Lokesh, P., Thrimurthulu, V., & Priya, L. M. (2019). Design of High Performance Pulse Generator to Perform Automatic Test in VLSI Circuits. i-manager's Journal on Electronics Engineering, 9(3), 26-31. https://doi.org/10.26634/jele.9.3.15953

Abstract

VLSI is the advanced technology mainly intended to incorporate million of transistors or ICs placed on a printed circuit board. As the technology advances, System on Chip (SoC) parameters are scaled to achieve high throughputs. Also different test patterns, Automatic Test Equipment, Automatic test pattern generators are important for testing memory, and device under Test ICs are required to find the faulty chips and hence nesecessary of Automatic Test pattern genetators, which help not only to increase the performance of the circuit, but also increase the life time of the component. In this paper, a high accuracy and wide data rate range pulse generator with 10 ps time resolution is presented to perform Automatic Test. The pulse generator works with two modules like Edge Combiner (EC) and Multi phase clock Generator (MPCG). Edge Combiner focuses on explaining the functionality of data range and timing resolution based on phase selection logic and also down counter. In Multi Phase Clock Generator, a Multiphase Oscillator (MPO) holds a ring oscillator scheme to extend operational frequency. Another advantage of multi phase oscillator is to reduce output phase errors if there is any layout mismatches. The design was implemented on 32 Nanometer CMOS technology with Virtex FPGA is the target Hardware device. Experimental results prove that the Area occupied and power consumed by the proposed pulse generators are found to have Low area and low power consumption, respectively.

Square Root Carry Select Adder Using MTTSPC D-Latch in 90nm Technology

Volume 9 Issue 3 March - May 2019

Research Paper

Square Root Carry Select Adder Using MTTSPC D-Latch in 90nm Technology

Prasad M.*, U. B. Mahadevaswamy**, Prashant Dandavatimath***

*_***Department of Electronics and Communication Engineering, Sri Jayachamarejendra college of Engineering, Mysuru, Karnataka, India.

Prasad, M., Mahadevaswamy, U. B., & Dandavatimath, P. (2019). Square Root Carry Select Adder Using MTTSPC D-Latch in 90nm Technology. i-manager's Journal on Electronics Engineering, 9(3), 14-25. https://doi.org/10.26634/jele.9.3.15267

Abstract

Adders have always been area of continual research in VLSI for high speed data path design. There have been different architectures proposed with design metrics and both the structures are compared for the parameters of power consumption and delay. In the proposed architecture using True single phase clocked (TSPC), D-Latch for square root (SQRT) carry select look ahead adder is compared with Multi-Threshold complementary metal oxide semiconductor (CMOS) D-latch based design. The design shows power dissipation reduction about 56% than that of MTCMOS. Further the proposed architecture using Multi-Threshold TSPCD-Latch for SQRT carry select look ahead adder is compared with Multi-Threshold CMOSD-latch based designs, the design with TSPC shows the power delay product reduction about 11%. Further, the proposed design is compared with different existing carry select adder designs. Hence, the proposed structure which has small area and less power consumption is implemented for 8-bit adder to reduce the power consumption and delay.

Implications of the Internet of Things (IoT) on Future Systems Integration

Volume 9 Issue 3 March - May 2019

Research Paper

Implications of the Internet of Things (IoT) on Future Systems Integration

Tom Page*

Department of Product Design, Nottingham Trent University, England.

Page, T. (2019). Implications of the Internet of Things (IoT) on Future Systems Integration. i-manager’s Journal on Electronics Engineering , 9(3), 1-13. https://doi.org/10.26634/jele.9.3.14701

Abstract

The Internet of Things (IoT) is currently experiencing a lag in consumer adoption potentially due to the industry led technology push with little consideration of consumer needs. This research aimed to assess current consumer awareness and adoption whilst in addition analysing future interest in IoT products or services and the barriers preventing adoption. Initial research involved a literature review of concept origins, technology, applications, data management, and standards for the IoT. Additional research was undertaken using a mixed methodology approach comprising of semistructured informal interviews and a structured online questionnaire survey both performed using members of the general public. The results revealed a current overall poor awareness and adoption of IoT products and services, however, a significant interest in future adoption. Various communication and technical barriers were also identified preventing current interest from actual adoption. The research discusses key insights from data collection which could aid in the removal of observed barriers. These insights involved increased consumer education, development of greater product benefit, and the introduction of standards to ensure interoperability. Application of these research findings could help enable increased widespread adoption of IoT products and service.

Energy Efficiency and Enhancement in Cognitive Radio Cellular Set-Up

Volume 9 Issue 2 December - February 2019

Research Paper

Energy Efficiency and Enhancement in Cognitive Radio Cellular Set-Up

G. Karpagarajesh*, S. Narmatha **, A. V. Niranjana ***, M. Ramya ****, P. Sivagami*****

*Assitant Professor, Department of Electronics and Communication Engineering, Government College of Engineering, Tamilnadu, India.

**_***** Undergraduate, Department of Electronics and Communication Engineering, Government College of Engineering, Tamilnadu, India.

Karpagarajesh,G.,Narmatha,S.,Niranjana,A.V.,Ramya,M.,Sivagami,P.(2019). Energy Efficiency and Enhancement in Cognitive Radio Cellular Set-Up.i-manager’s Journal on Electronics Engineering,9(2),36-44. https://doi.org/10.26634/jele.9.2.15397

Abstract

As the quantity of mobile clients increments exponentially, improving the pectrum effectiveness was more important by keeping in mind the end goal to suit more clients. In this paper, by abusing the collaboration between Principle Base Stations (PBS) and Minor Base Stations (MBS), another vitality range exchanging model was proposed to upgrade the vitality and also range proficiency of cell systems. By utilizing cognitive radio, PBS shares some part of their authorized range with MBS. MBS in return to give information administration to the rule clients under their scope. Efficient power Energy Attentive Request (GEAR) and Adaptive Request Allocation (ARA) calculations are the calculations to accomplish a decent estimation of the ideal arrangement in less time.

Contemplation on Smart Toll Collection Strategies and Enhancement

Volume 9 Issue 2 December - February 2019

Research Paper

Contemplation on Smart Toll Collection Strategies and Enhancement

Mohil Kumar Verma*, Rakesh Anand**, Amit Kumar Barnwal***, Surekha Bhusnur****

*_***UG Scholar, Department of Electrical and Electronics Engineering, Bhilai Institute of Technology, Durg, (C.G), India.

****Professor,Department of Electrical and Electronics Engineering, Bhilai Institute of Technology, Durg, (C.G), India.

Verma,M.,Anand,R.,Barnwal,A.,Bhusnur,S.(2019).Contemplation on Smart Toll Collection Strategies and Enhancement.i-manager’s Journal on Electronics Engineering,9(2),29-35. https://doi.org/10.26634/jele.9.2.15112

Abstract

The problem of managing smart toll lanes is one of the crucial topics of researchers and transportation industry. This paper provides an insight to various strategies involved in Smart Toll Collection System (STCS). One of the most widely used techniques for STCS is the Radio Frequency Identification (RFID) technique. A small prototype hardware realization of STCS is delineated to make the basics discernible. This paper describes the toll collection system based on distance travelled by the vehicle using RFID technology. The vehicle will hold a unique identification number assigned to the vehicle by traffic governing authority. All basic information as well as prepaid account details to ensure payment against toll tax incurred, is stored in the data base of the STCS. The unique tag number is read by the RFID reader at both entry and exit of the toll road and gate number will be stored in data base. At the time of exit, the distance will be calculated by the microcontroller. The billing amount is then displayed, balance is deducted from the prepaid balance, and new balance is updated. This paper is a short communication to enable a novice to decipher the details involved in STCS in a facile manner.

Low Power Design for Testability Implementation for Asynchronous FIFO

Volume 9 Issue 2 December - February 2019

Research Paper

Low Power Design for Testability Implementation for Asynchronous FIFO

Madhu Kumar Patnala*, R. Nagendra**

*_** Assistant Professor (SL), Center for VLSI & Embedded Systems, Department of Electronics and Communication Engineering, SreeVidyanikethan Engineering College, (Autonomous) Tirupati, Andhra Pradesh, India.

Patnala,M.K.,Nagendra,R.(2019).Low Power Design for Testability Implementation for Asynchronous FIFO.i-manager’s Journal on Electronics Engineering,9(2),24-28. https://doi.org/10.26634/jele.9.2.15142

Abstract

A First in First out (FIFO) is used as a memory buffer between two asynchronous systems with simultaneous write and read access to and from the FIFO, where these accesses being independent of one another. Sequential operation of FIFO is particularly useful for implementing system level functions like Packet Buffering, Frequency Coupling, and Bus Matching. Asynchronous FIFO is a memory file, which uses synchronization for reading and writing with different clocks, by performing the conditions of over-run and under-run. In essence, the transfer of data from read domain to write domain with different frequencies. To generate overrun and under-run status flags, the synchronization takes place with the help of “preceding operation”of both the write and read pointers. In this design, the gray code converters are used to reduce switching activity and the low power Design for Testability (DFT) technique was applied by considering the two phases that is scan insertion and ATPG Simulations. This design is executed by using synthesizable VERILOG (Register Transfer Level) RTL Code and verified with Xilinx ISE simulator.

IoT Based Smart Health Monitoring System

Volume 9 Issue 2 December - February 2019

Research Paper

IoT Based Smart Health Monitoring System

U. B. Mahadewaswamy*, Zaibabuktiyar Durgad**

*Professor, Department of Electronics and Communication, JSSS&TU, Mysuru, Karnataka, India.

**PG Scholar, Department of Electronics and Communication, JSSS&TU, Mysuru, Karnataka, India.

Mahadevaswamy,U.B., Durgad,Z.,(2019).IoT Based Smart Health Monitoring System.i-manager’s Journal on Electronics Engineering,9(2),8-23. https://doi.org/10.26634/jele.9.2.14867

Abstract

Globalization around the world has led to a number of spontaneous technologies. Among them artificial intelligence is one such technique which can be implemented through IoT. The aim of this work is to design and develop a system which performs the tasks of measurement of vital parameters, such as temperature, blood pressure, and heart rate. The measured values are continuously updated on ThingSpeak server using Wi-Fi module and in case of abnormalities, the information is conveyed to the concerned doctor through SMS using GSM module. An alert call is also initiated to the doctor after a couple of minutes. The system also has an inbuilt pill tracker unit, which alerts the patient at right time to take the prescribed tablet and it also warns the patient in case of wrong tablet selection. Simultaneously, the message regarding wrong tablet selection is sent to the caretaker. The system is also programmed to measure and categorize the nature of blood pressure. The performance of the system with respect to the measurement of blood pressure, heart rate, and temperature is evaluated under the supervision of a qualified physician. The readings recorded by the system are compared with the observations recorded by the physician using conventional methods. The application of the system as pill tracker is studied by considering a patient with multiple ailments.

A Comparison of CNTFET Models through a Simulation Study of Digital Circuits

Volume 9 Issue 2 December - February 2019

Research Paper

A Comparison of CNTFET Models through a Simulation Study of Digital Circuits

Roberto Marani*, Anna Gina Perri**

*Researcher, Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council, Italy.

**Full Professor and Head of Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, Bari, Italy.

Marani,R.,Perri,A.G.(2019).A Comparison of CNTFET Models through a Simulation Study of Digital Circuits.i-manager’s Journal on Electronics Engineering,9(2),1-7. https://doi.org/10.26634/jele.9.2.15180

Abstract

In this paper, the authors present a simulation study in order to carry out static and dynamic analysis of CNTFET-based digital circuits, in the semi-empirical compact model for CNTFETs, which was already proposed with, both the quantum capacitance effects and the sub-threshold currents. To verify the validity of the obtained results, they are compared with those of the Stanford-Source Virtual Carbon Nanotube Field-Effect Transistor (VS-CNFET) model. This comparison is made through some simulations of digital circuits. In particular they have considered XOR gate, but emphasizing that the proposed procedure can be applied to any logic gate based on CNTFET. As regards the static conditions, the two models behave in a manner virtually identical, while, as regards the dynamic analysis, there is a remarkable differences between two models in terms of propagation delays and rise and fall times.

Automatic Accident Detection and Tracking of Vehicles by Using MEMS

Volume 9 Issue 1 September - November 2018

Research Paper

Automatic Accident Detection and Tracking of Vehicles by Using MEMS

Vulavabeti Raghunath Reddy*, Chandra Mohan Reddy Sivappagari**

* Post Graduate, Department of Electronics and Communication Engineering, JNTUA College of Engineering, Pulivendula,Andhra Pradesh, India.

** Associate Professor, Department of Electronics and Communication Engineering, JNTUA College of Engineering, Pulivendula,Andhra Pradesh, India.

Reddy,V.R.,K.,& Sivappagari,C.M.R. (2018). Automatic Accident Detection and Tracking of Vehicles by Using MEMS. i-manager’s Journal on Electronics Engineering , 9(1), 34-40. https://doi.org/10.26634/jele.9.1.14771

Abstract

The improvement of knowledge and substructure takes through our inhales natural. The arrival of equipment consumes improved the road traffic exposures and the road accident take place regularly which practicalities enormous injury of lifetime and belongings because of the concentrated emergency facilities. Our development resolve deliver an right justification to this problem. An accelerometer can be recycled popular a car apprehension submission so that hazardous motivating can be searched. It container be rummage-sale as a crash or rollover detector of the vehicle over and subsequent an accident, an accidents can be recognized with a help of an accerlometer sensor. The main aim of implemented this project identification of accidents through vibrations the sensor is notice the signals of vehicle moves, the MEMS sensor is pass the signal to the ARM controller to performed action. The signal is send to the GSM module it gives accident location of information to the rescue team or pre-defined numbers after receiving the message rescue or predefined numbers know the accident location. Then takes the immediate action.

QoS Control for Wireless Video Communication - A Survey

Volume 9 Issue 1 September - November 2018

Research Paper

QoS Control for Wireless Video Communication - A Survey

K. Maheswari*, N. Padmaja**

* Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Anantapur, Andhra Pradesh, India.

** Professor, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, Andhra Pradesh, India.

Maheswari,K., & Padmaja,N. (2018). QoS Control For Wireless Video Communication - A Survey . i-manager’s Journal on Electronics Engineering , 9(1), 27-33. https://doi.org/10.26634/jele.9.1.14810

Abstract

4G mobile phones are able to perform video coding and streaming over wireless networks, but are often constrained by the energy supply and end-to-end delay requirements. Video transmission via wireless channels with good Quality of Service (QoS) is still strenuous problem as it is a difficult task to deliver video content through limited bandwidth and error prone networks. In a real time wireless video communication system, the capture-to-display delay would significantly affect the overall video reception quality. To study, control, and optimize the quality of service parameters in the recent video transmission schemes, the DRDO for the wireless video communication system is extented and a novel control algorithm is proposed by investigating the allocation of capture-to-display delay to different delay components. Causes of end-to-end delay are identified and quantified, where the average end-to-end distortion under the transmission rate and end-to-end delay are considered by a joint selection of both source coding and channel coding parameters. To guarantee the Quality of Service (QoS), different service levels are specified for various stream of traffic in terms of delay, distortion, power, throughput, rate, and packet loss. This survey highlights, the tradeoff between various QoS parameters in the area of wireless video communication systems and quality of the reproduced picture.

Design, Implementation and Simulation of Patient Monitoring System using Steady State Visual Evoked Potential Signal based on LABVIEW

Volume 9 Issue 1 September - November 2018

Research Paper

Design, Implementation and Simulation of Patient Monitoring System using Steady State Visual Evoked Potential Signal based on LABVIEW

Harsha K. M.*, Shalini Shravan**

* BE Graduate, Department of Electronics and Communication Engineering, K.S. School of Engineering and Management, VTU,Bangalore, Karnataka, India.

** Assistant Professor, Department of Electronics and Communication Engineering, K.S. School of Engineering and Management, VTU,Bangalore, Karnataka, India.

Harsha,K.M.,&Shravan,S. (2018). Design, Implementation and Simulation of Patient Monitoring System Using Steady State Visual Evoked Potential Signal Based On LabVIEW.i-manager’s Journal on Electronics Engineering ,9(1),21-26. https://doi.org/10.26634/jele.9.1.14807

Abstract

Paralyzed people find it difficult to communicate their intent to serve outside world. Hence, this work provides a Mind Controlled communication system that uses Brain Computer Interface which can bypass different communication channels like neurons’ electrical activity, muscles, and thoughts to supply direct communication and management between the physical devices and human brain by translating dissimilar patterns of brain activity into instructions followed by the conversion of predefined text on the screen into voice. The proposed system consists of: Amplifier Filter circuits and LabVIEW software for signal processing and acquisition. The main aim of this work is to develop a brain computer interface system called BCI system that allows the paralyzed people to communicate their intention without any difficulty, provided it is more superior which may assist disabled folks in their everyday life. Different messages are put up on the visual stimulation screen and made to flicker at different frequencies. When patient looks at one of the flickering frequency on the screen, the same frequency is generated in the visual cortex of the human brain and the frequency is then determined by signal acquisition system and translates the predefined assigned message to voice.

Atmospheric Radar Signal Processing Using Hybrid Window Functions

Volume 9 Issue 1 September - November 2018

Research Paper

Atmospheric Radar Signal Processing Using Hybrid Window Functions

G. Chandraiah *, T. Sreenivasulu Reddy**

* Research Scholar, Department of Electronics and Communication Engineering, S.V.U. College of Engineering, S.V. University, Tirupati,Andhra Pradesh, India.

** Professor, Department of Electronics and Communication Engineering, S.V.U. College of Engineering, S.V. University, Tirupati,Andhra Pradesh, India.

Chandraiah,G.,& Reddy,T.S.(2018) Atmospheric Radar Signal Processing Using Hybrid Window Functions. i-manager’s Journal on Electronics Engineering ,9(1), 14-20. https://doi.org/10.26634/jele.9.1.14427

Abstract

The MST radar is situated at National Atmospheric Research Laboratory (NARL), Gadanki, Andhra Pradesh. This radar is used to investigate the atmospheric dynamics in the regions of Mesosphere, Stratosphere, and Troposphere (MST). MST radar was developed with an active phased antenna array consisting of 1024 Yagi-Uda antenna elements and operated by a frequency of 53 MHz. In this article, the authors introduce new hybrid window functions by using a combination of Kaiser and Blackman windows. The new hybrid window functions exhibit low side lobe levels and narrow beam width of main lobe so that the spectral leakage is minimum. The proposed window based algorithms has been applied to MST radar time series data to compute Doppler power spectrum. After computing Doppler spectrum, the wind parameters like Zonal U, Meridional V, and Wind velocity W can be calculated from the Doppler profile. The obtained wind velocity components of the MST radar data is validated through the Global Positioning System (GPS) Radiosonde data.

Simulation and Performance Comparison of Variable Speed Multi-Phase PMSM Machines

Volume 9 Issue 1 September - November 2018

Research Paper

Simulation and Performance Comparison of Variable Speed Multi-Phase PMSM Machines

Khadim Moin Siddiqui*, Amreen Fatma**, Mohd Khursheed Siddiqui***

* Associate Professor and Head, Department of Electrical Engineering, Guru Nanak Institute of Engineering & Management, Hoshiarpur,Punjab, India.

** Postgraduate, Department of Instrumentation and Control, Integral University, Lucknow, Uttar Pradesh, India.

*** Associate Professor, Department of Electrical Engineering, Integral University, Lucknow, Uttar Pradesh, India.

Siddiqui,K.M., Fatma,A.,& Siddiqui,M.K.(2018). Simulation and Performance Comparison of Variable Speed Multi-Phase PMSM Machines. i-manager’s Journal on Electronics Engineering , 9(1), 7-13. https://doi.org/10.26634/jele.9.1.15120

Abstract

In the present time, the multi-phase Permanent Magnet Synchronous Machines (PMSMs) are being popular in the industries with efficient performance. In future, the multi-phase Permanent Magnet (PM) synchronous machines may be used in the variable speed drive applications, especially in renewable energy generation. Therefore, an accurate simulation model is needed for variable speed applications of PMSMs. Therefore, in this paper, an attempt has been made to make variable speed PMSMs simulation models in the latest MATLAB/Simulation environment with effective performance. The three phase and five phase variable speed PMSM machines models have been developed and both the performances have been compared. For performance comparison, three motor parameters have been used; these are stator currents, rotor speed, and electromagnetic torque. In the simulation models, two control loops have been used for efficient performance of the motor. The inner loop is used to control the speed of the motor and outer loop is used to control stator currents. The PI controller has also been used for motor controlling purpose. Finally, the authors state that the five phase variable speed PMSM motor model gives encouraging results as compared to three phase PMSM motor.

An Article on CNC Upgradation

Volume 9 Issue 1 September - November 2018

Article

An Article on CNC Upgradation

Shradha Sanjay Sandanshiv*, Swapnali Dayanand Shete**, Shraddha Shrimant Shinde***, M. M. Narkhede****

*-*** BE Graduate, Department of Electronics and Telecommunication Engineering, Pimpri Chinchwad College of Engineering, Nigdi, Pune,Maharashtra, India.

**** Assistant Professor, Pimpri Chinchwad College of Engineering, Nigdi, Pune, Maharashtra, India.

Sandanshiv,S.S., Shete,S.D., Shinde,S.S., & Narkhede,M.M.(2018). A Review Paper On CNC Upgradation. i-manager’s Journal on Electronics Engineering, 9(1), 1-6. https://doi.org/10.26634/jele.9.1.14425

Abstract

This paper deals with the upgradation of CNC machine and its flexibility for modern technologies. In this paper, designing of control panel and its implementation is discussed. Different components are mounted in control panel to protect the system in case of power failure and protect motors against phase down. Almost all the industries use PLCs now-a-days because it is highly compatible, reduces wiring, and makes the design more compact and reliable. This is as up-gradation of CNC machine. Generally, PLCs are programmed in “ladder logic”, which strongly resembles a schematic diagram of relay logic. Different ladder logics are developed for performing different operations. This article can be extended further by emerging it with IIoT, i.e. Industrial Internet of Things, where we can monitor CNC machines from remote place.

Performance Metrics and Temperature Variability in a 16 nm Spacer FinFET

Volume 8 Issue 4 June - August 2018

Review Paper

Performance Metrics and Temperature Variability in a 16 nm Spacer FinFET

Sangeetha Mangesh*, Krishan K. Saini**, P. K. Chopra***

* Assistant Professor, Department of Electronics & Communication Engineering, JSS Academy of Technical Education, Noida, Uttar Pradesh .India

** Chief Scientist, National Physical Laboratory, New Delhi, India .

*** Professor and Head, Department of ECE & EI, Ajay Kumar Garg Engineering College, Ghaziabad, Uttar Pradesh, India.

Mangesh. S., Saini. K. K and Chopra. P. K (2018). Performance Metrics and Temperature Variability in a 16 nm Spacer FinFET. i-manager's Journal on Electronics Engineering, 8(4), 41-49. https://doi.org/10.26634/jele.8.4.13993

Abstract

Driven by Moore's law, the scaling of devices has reached nanoscale. The journey of miniaturizations has encountered several challenges to attain desired electrical characteristics to meet the demand in the era of information technology. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, being a major building block for designing both analog and digital circuits in IC design technology, has consequently undergone multiple structural variations to meet these challenges.

Planar as well as SOI multi-gate MOSFET devices are the front runners, amongst them. These devices have better controlling ability due to inherent advantage of multi-gate technology. This paper, carries out an analysis of an improved Fin Field Effect Transistor (FinFET) device designed for 16 nm channel length. Its performance metrics are compared with a regular design. A 16 nm FinFET design using nitride layers is implemented using Technology Computer Aided Design (TCAD) and analysis of threshold voltage, transconductance, Subthreshold Slope (SS), leakage current, charge density variations along fin, quasi Fermi Energy variations of electrons, electron net electron charge, carrier recombination, and mobility along the channel and an ability to withstand temperature is carried out. Timing analysis is also carried out implementing a resistive load inverter employing both the devices. The results are analyzed and compared with simple planar counterpart along with justification claiming the improved spacer FINFET design along with its limitations.

Analysis of selectively filled Ethanol holes in octagonal ring of photonic crystal fiber

Volume 8 Issue 4 June - August 2018

Research Paper

Analysis of selectively filled Ethanol holes in octagonal ring of photonic crystal fiber

Vikas Sahu**, Akash Joshi***

*,*** PG Scholar, Department of Electronics & Telecommunications Engineering, Shri Shankaracharya Technical Campus, Bhilai, Chhattisgarh, India.

** Assistant Professor, Department of Electronics & Telecommunications Engineering, Shri Shankaracharya Technical Campus, Bhilai, Chhattisgarh, India.

Panda. S. G., Sahu. V and Joshi. (2018). Analysis of Selectively Filled Ethanol Holes in Octagonal Ring of Photonic Crystal Fiber. i-manager's Journal on Electronics Engineering, 8(4), 34-40. https://doi.org/10.26634/jele.8.4.14783

Abstract

This paper proposes the analysis of various parameters after simulations of Photonic crystal fibers having air holes arranged in octagonal shape. Some of the air-holes replaced by some other liquid of refractive index differ from air to achieve more effective responses. This Octagonal Photonic Crystal Fiber (O-PCF) consists of four rings in which the air holes are placed. Four holes in the innermost ring of O-PCF are filled with Ethanol instead of air. The parameter calculations are done by varying the hole diameters, pitch values, and wavelengths while keeping the perfectly matched layer (PML) values constant. COMSOL Multiphysics is the software platform used to design these proposed structures, which uses Finite Element Method (FEM). The calculation of confinement loss and graphical representation are done in MATLAB. The advantage of taking ethanol as a substitute of air is that the confinement loss is reduced as compared to the confinement loss with only air hole PCF structures.

Implementation of Low power High Speed 64-bit Memory Unit using 8T SRAM Cell at 70 nm Technology

Volume 8 Issue 4 June - August 2018

Research Paper

Implementation of Low power High Speed 64-bit Memory Unit using 8T SRAM Cell at 70 nm Technology

Pushpa Raikwal*, Besik G. Eristavi**, Ajay Verma***

* Research Scholar, Department of Electronics and Telecommunication Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, Madhya Pradesh, India.

** Assistant Professor, Department of Electronics and Instrumentation Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, Madhya Pradesh, India.

*** Professor and Head, Department of Electronics and Instrumentation Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, Madhya Pradesh, India.

Raikwal. P., Neema. V and Verma. A. (2018). Implementation of Low Power High Speed 64-Bit Memory Unit using 8T SRAM Cell at 70 nm Technology. i-manager's Journal on Electronics Engineering, 8(4), 26-33. https://doi.org/10.26634/jele.8.4.14782

Abstract

Design and implementation of memory devices are becoming a challenge for the memory designers due to various limitations. Leakage power dissipation and low data stability are the main constraints, while designing memory integrated circuits. In this paper, a new 8T Static Random Access Memory (SRAM) cell, that adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high data stability. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit. It shows the high data stability 343 MV and 329 MV during read and hold state, respectively. Additionally, this paper contains 64-bit memory unit of the proposed 8T SRAM cell (8 x 8) array. The array comprises of row decoder, column decoder, and sense amplifier. The proposed 8T SRAM cell is 16.45X and 43.78X fast during read 0 and read 1 operations, respectively, while during write 0 and write 1 operations the delay is reduced up to 8.05% and 8.46%, respectively when compared with (8 x 8) array of 6T SRAM cell. During read 0 and read 1, it is fast by 16.45X and 43.78X, respectively. The average power consumption during read 1/0 and write 1/0 operations are 99.5% /60.05% and 99.61% /59.82% less as compare to 6T SRAM array, respectively.

Design of Dual-Power-Supply-SRAM and Measure of Active and Standby Mode Power by using BL Calculator

Volume 8 Issue 4 June - August 2018

Research Paper

Design of Dual-Power-Supply-SRAM and Measure of Active and Standby Mode Power by using BL Calculator

P. Lokesh*, T.Munireddy**, Olga O. Tsurtsumia***

*,*** Assistant Professor, Department of Electronics and Communication Engineering, VEMU Institute of Technology, Andhra Pradesh, India.

** Associate Professor, Department of Electronics and Communication Engineering, VEMU Institute of Technology, Andhra Pradesh, India.

Lokesh. P and Munireddy.T and Pesha. J. V. (2018). Design of Dual-Power-Supply-SRAM and Measure of Active and Standby Mode Power by Using Bl Calculator. i-manager's Journal on Electronics Engineering, 8(4), 19-25. https://doi.org/10.26634/jele.8.4.13995

Abstract

In this paper, an efficient Dual power supply Static Random Access Memory (SRAM) is designed which reduces power consumption in Active and Standby mode. To achieve this, different circuit techniques is introduced to minimize both power modes particularly at room temperature. If the circuit operates in Active mode, a Bit Line (BL) power calculator is used uniformly to set the supply voltages between the cells or nets. In the stand-by mode, a digitally controllable retention circuit is used to regulate the supply voltages with small control power. Efficient circuit techniques of SRAM reveal the power reduction of 27% in Active mode and 85% in Stand-by mode. The design is carried out in Code Composer Studio (CCS) as the software environment and MSP430G2553 is the target Hardware device. When compared with the conventional schemes, the proposed design reduces power consumption at a greater extent.

De-noising of CT Images using Combined Bivariate Shrinkage and Enhanced Total Variation Technique

Volume 8 Issue 4 June - August 2018

Research Paper

De-noising of CT Images using Combined Bivariate Shrinkage and Enhanced Total Variation Technique

Devanand Bhonsle*, Vivek Kumar Chandra**, G.R.Sinha***

* Senior Assistant Professor, Department of Electrical and Electronics Engineering, SSTC-SSGI, Faculty of Engineering & Technology, Bhilai, Chhattisgarh, India.

** Professor and Head, Department of Electrical and Electronics Engineering, Chhatrapati Shivaji Institute of Technology, Durg, Chhattisgarh, India.

*** Adjunct Professor, IIIT Banglore, Karnataka, India.

Bhonsle. D., Chandra. V. K and Sinha. G. R. (2018). De-Noising of Medical Images Using Combined Bivariate Shrinkage and Enhanced Total Variation Technique. i-manager's Journal on Electronics Engineering, 8(4), 12-18. https://doi.org/10.26634/jele.8.4.14426

Abstract

The authors have developed a combined approach to reduce the effect of noise from the medical images. Noises are generally originated due to physical processes of imaging rather than in the tissue textures. Various types of noise signals, viz. photon, electronics, quantization, etc., often contribute to degrade the image quality. In general, the overall noise is assumed to be additive with a zero-mean, constant-variance Gaussian distribution, which is commonly known as Additive White Gaussian Noise (AWGN). In this paper, de-noising methods are applied on Computed Tomography (CT) images using a proposed combined method which combines bivariate thresholding and enhanced total variation methods using wavelet based image fusion technique. This method provides better results in terms of Peak Signal to Noise Ratio (PSNR).

A Comparative Study of Hetero Structure Devices for Electronic Applications

Volume 8 Issue 4 June - August 2018

Research Paper

A Comparative Study of Hetero Structure Devices for Electronic Applications

Roberto Marani*, Anna Gina Perri**

* Researcher, Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council of Italy.

** Professor of Electronics and Head of Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, Bari, Italy.

Marani. R and Anna Gina Perri. (2018). A Comparative Study of Hetero Structure Devices for Electronic Applications. i-manager's Journal on Electronics Engineering, 8(4), 1-11. https://doi.org/10.26634/jele.8.4.14196

Abstract

In this paper, the authors present a comparison through a simulation study, among different hetero structure devices, like Metal Semiconductor Field Effect Transistor (MESFET), High Electron Mobility Transistor (HEMT), and Tunnel Field Effect Transistor (TFET), with reference to their applications in electronic field. In particular, MESFET and HEMT present good performance in power amplifiers and they are characterized by high mobility of the charge carriers that allows to consume less at high frequency. TFET is the newest experimental device, which has a very powerful application in logic circuits, ultra low-power specific analog ICs with better temperature strength and low-power SRAM.

FPGA Implementation of Reversible Logic Gates

Volume 8 Issue 3 March - May 2018

Research Paper

FPGA Implementation of Reversible Logic Gates

Gowthami P.*, R.V.S. Satyanarayana**

* Research Scholar, Department of Electronics and Communication Engineering, SV University College of Engineering, Tirupati, Andhra Pradesh, India.

** Professor, Department of Electronics and Communication Engineering, SV University College of Engineering, Tirupati, Andhra Pradesh, India.

Gowthami. P and Satyanarayana. R.V.S. (2018). FPGA Implementation of Reversible Logic Gates. i-manager's Journal on Electronics Engineering, 8(3), 45-62. https://doi.org/10.26634/jele.8.3.14389

Abstract

Reversible logic is one of the emerging research areas having its application in the fields of Quantum computing, Optical computing, DNA computing, Nanotechnology, Cryptography, Bioinformatics etc. Reversible Logic has attained importance in the recent developments of high speed and low power digital systems. This has led to present data relating to the different reversible logic gates which are available in the literature. The Verilog Hardware Description Language (HDL) is used to code the reversible gates. The simulation and synthesis are carried out in Xilinx 14.3 Integrated Synthesis Environment (ISE).

Design and Analysis of Microstrip Antenna Using RBF-NN for Multiband Operation

Volume 8 Issue 3 March - May 2018

Research Paper

Design and Analysis of Microstrip Antenna Using RBF-NN for Multiband Operation

Mohd Gulman Siddiqui*, Abhishek Kumar Saroj**, Rohini Saxena***, Devesh Tiwari****, J.A. Ansari*****

*-**** Research Scholar, J.K. Institute of Applied Physics and Technology, University of Allahabad, Allahabad, Uttar Pradesh, India.

***** Professor, Department of Electronics Engineering, University of Allahabad, Allahabad, Uttar Pradesh, India.

Siddiqui. M. G., Saroj. A. K., Saxena. R., Tiwari. D and Ansari. J.A. (2018). Design and Analysis of Microstrip Antenna Using RBF-NN for Multiband Operation. i-manager's Journal on Electronics Engineering, 8(3), 36-44. https://doi.org/10.26634/jele.8.3.14390

Abstract

The analysis of Multiband Microstrip Antenna (MSA) using Neural Network (NN) through Radial Basis Function (RBF) has been descibed in this paper. Two parallel slots have been inserted on the patch of MSA. The estimation of bandwidth with the variation of these slots has been trained and tested using ANN. The antenna resonates at frequencies 2.465 GHz, 3.455 GHz, and 5.17 GHz with obtained fractional bandwidth of 5.601 MHz, 8.09 MHz, and 16.80 MHz, respectively. The geometry of antenna is then simulated using HFSS simulation software. The results are measured and tested using vector network analyzer. The frequency bands meet the design specification of covering the WLAN and WiMAX application at C-band.

Compact Multiband Planar Inverted L Patch Antenna Array for Smartphones

Volume 8 Issue 3 March - May 2018

Research Paper

Compact Multiband Planar Inverted L Patch Antenna Array for Smartphones

* Associate Professor, Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College, Bidar, Karnataka, India.

Dakulagi. V. (2018). Compact Multiband Planar Inverted L Patch Antenna Array for Smart Mobile Phones. i-manager's Journal on Electronics Engineering, 8(3), 32-35. https://doi.org/10.26634/jele.8.3.14415

Abstract

Microstrip antennas are the ones that fulfill most of the wireless system requirements. These antennas are widely used on base stations as well as handsets. The microstrip patch antennas have increasingly wide range of applications in the wireless communication system due to their great advantages. Planar Inverted L Patch (PILP) Antenna is a good candidate for achieving compact microstrip antennas. In addition to compact operation, this design is also suitable for dual-frequency operation. To satisfy the needs of certain wireless communication systems, it is required to design and develop the antenna arrays to obtain the increase in gain and enhancement in the bandwidth. The 2x1 element arrays of microstrip line fed shorted patch antennas are developed. The experimental study shows that the arrays offer considerable increase in gain and enhancement in the bandwidth.