Binary Morphology With Image Compression And Cryptography

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : Binary Morphology With Image Compression And Cryptography

Author Name : Ponshankar B, Swaranambigai.R

Synopsis :

Ponshankar and his co-author Swaranambigaidesigned a Mathematical Morphology (MM) method for binary images, and extended thatfor applying to many different image representations.The stall-free low-complexity architecture has been proposed for taking advantage of the morphological duality principle and Structuring Element (SE) decomposition. The simulation results are more convenient than the mixed grain architectureand providean efficient blind binary image authentication scheme.

For more details:

imanagerpublications.com

Performance Comparison of Carbon Nanotube, Graphene Nano Ribon and Silicon Nanowire Transistors

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : Performance Comparison of Carbon Nanotube, Graphene Nano Ribon and Silicon Nanowire Transistors

Author Name : S. B. Siddique, T. M. Faruki , B.C. Sarkar , Md. Mahmudul Hasan

Synopsis :

Siddique et.alanalyzed the performance potential of ballistic CNT, Graphene and Silicon Nanowire(SiNW) field effect transistors for future high-performance applications. The simulation is carried out on single sub-band top of the barrier model and the common off-current value is set as 10nA.The result shows that the CNT transistor is a good amplifier and the transconductance is high compared to GNR and SiNW transistors by showing higher frequency performance and higher transconductance.

For more details:

imanagerpublications.com

Performance Analysis of Low-Density Parity-Check Codes for M-QAM Systems

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : Performance Analysis of Low-Density Parity-Check Codes for M-QAM Systems

Author Name : HIRALD DWARAKA PRAVEENA, C.Subhas , padmaja nimmagadda

Synopsis :

Hirald Dwaraka Praveena et.al proposed a M-QAM scheme for achieving spectral efficiency of high order modulation. For low complexity decoding, low cost and low bit-error rate LDPC (Low-Density Parity-Check) codes are chosen using encoding and decoding methods. Error Correcting Codes (ECCs) are determined for detecting and correcting errors for increasing the system throughput, speed and reducing power consumption. The simulated results are more reliable compared to Turbo codes.

For more details:

imanagerpublications.com

A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity

Author Name : sandhiya vijayakumar, S. Karthick , M.Valarmathy

Synopsis :

Sandhiya et.al developed CSM and PSM approaches for implementing reconfigurable higher order filters with low complexity. Greedy CSE (Common Subexpression Elimination) algorithm is applied for achieving reduction in complexity. Binary based fir filter gives 33% better reduction than CSD based CSE method. Finally, mentorgraphics tool and Xilinx(synthesis) are used to simulate and compare the results of CSD and Binary based CSE, greedy, VCSE and HCSE techniques for finding the best one adder reduction method in low complexity FIR filter.

For more details:

imanagerpublications.com