Implementation and Analysis of Adaptive Algorithm with Shadow Technique on FPGA

Vol. 6  Issue 4
Year: 2016
Issue:Jun-Aug 
Title:Implementation and Analysis of Adaptive Algorithm with Shadow Technique on FPGA
Author Name:M. Koteswara Rao and I. Santhi Prabha 
Synopsis:

This paper explains the implementation based on adaptive filter algorithm with shadow technique, which belongs to the class of LMS algorithm on FPGA. The objective of this paper is to cancel out additive noise due to the effect of environmental conditions in the communication system. The additive noise is one of the major problems in the communication, especially in the digital electronic circuits design these days. Generally, the coefficient of filter updation is not in a basic filter time to time, as it may be an effect on the desired information. By updating coefficient of filter time to time, this problem could be eradicated and by increasing the number of iterations for the filtering process, it would give an efficient result. The popular method used to cancel out the additive noise in the communication systems is the Least Mean Square (LMS) algorithm. Here, a novel shadow based technique is employed in fixed LMS adaptive filter for improving the spectral characteristics like Side Lobe Attenuation (SLA), Main Lobe Width (MLW), Side Lobe Fall of Ratio (SLFR) of the filter by changing the feedback factor 'β'. In this project, it is found that the performance of shadow based fixed LMS is improved when compared to the existed fixed LMS in terms of signal-to-noise ratio (SNR) and Mean Squared Error (MSE) done with the help of MATLAB tool, and this proposed project was implemented on FPGA with utilization of minimum number of logic gates, flip flops, LUT's, and registers that are operated at maximum frequencies. This paper also compares the number of flip flops, logic gates, LUT's, and registers utilized for different resources in the family of FPGA. In real time applications, the adaptive filter algorithm implementation on FPGA plays a crucial role, especially in the DSP processors for effective communication. By introducing the concept of shadow technique in the adaptive filtering, the additive noise would be suppressed in the communication systems. The core FPGA is designed such that, it can be implemented in any brand of SoPC. In this paper, SPARTAN 3E and Vertex 4 are the application platform of FPGA. The achieved results gives an improvement in area resource utilization, convergence rate, speed, and performance in design pure LMS hardware core. Implementing the LMS adaptive filter algorithm on FPGA is achieved in VERILOG hardware description languages.

Analysis of Modular Multipliers

Vol. 6  Issue 4
Year: 2016
Issue:Jun-Aug 
Title:Analysis of Modular Multipliers
Author Name:Tallaka Yamini, A.B. Yadav and Koppala Neelima
Synopsis:

This paper proposes a simple and efficient Modular Multiplication algorithm. Montgomery modular multipliers can be implemented accordingly. Based on the Montgomery technique, both SCS and FCS are used by the Carry save format and also the modified SCA. The proposed SCS have used CCSA. To increase the performance of the cryptosystem, the modular multiplication is interleaved by serial and parallel radix-4 modular multipliers and also the same for normal multiplication. By comparing this technique, critical path and clock cycles are reduced. Now these techniques are used in Verilog HDL Virtex-3E using Xilinx ISE 14.5 design suite.

Parallel Prefix Adders based Matrix-Vector Multiplier for Iterative Methods in CDMA Communication Systems

Vol. 6  Issue 4
Year: 2016
Issue:Jun-Aug 
Title:Parallel Prefix Adders based Matrix-Vector Multiplier for Iterative Methods in CDMA Communication Systems
Author Name:Budarapu Prathyusha and G. Naresh
Synopsis:

Iterative methods are the basic building blocks of communication systems and represent a dominating part of the system. So, it is necessary for the careful design of the system for optimal performance. The most computationally expensive operations in the iterative methods are the matrix-vector multiplications. Therefore, it is important to reduce the number of matrix-vector multipliers in the design to reduce the hardware consumption. In this paper, the authors have proposed a design of matrix-vector multiplier that can be used to implement the widely adopted iterative methods. By using Brent Kung adder, the computational performance is increased by reducing the hardware consumption. The proposed design uses the sparse structure of the matrix and the spreading code matrices have equal magnitude entries. The design and simulation results are promising and are shown to satisfy the most modern communication system requirements.

A Novel Design of Efficient Adaptive FIR Filter by using A1CSAS

Vol. 6  Issue 4
Year: 2016
Issue:Jun-Aug 
Title:A Novel Design of Efficient Adaptive FIR Filter by using A1CSAS
Author Name:B. Rajani and T. Krishna Murthy
Synopsis:

The Adaptive FIR filters plays an important role in Digital Signal Processing. This paper presents a Novel Design of efficient Adaptive FIR filters by using A1CSAS. Many of the devices are powered by batteries. Therefore, there is a need for an excellent compromise between performance and power consumption. Usually, either delay or power is prioritized in this paper. These requirements are conflicting normally; when one requirement is optimized the other is affected. The delay is reduced by using carry select adder with add one select block (A1CSAS) in the inner product of the Adaptive FIR filter. Adaptive FIR filters are performed by Distributed Arithmetic process because it is an easy and simple method. Inner products in the DA table are calculated by using Distributed Arithmetic process. The add one carry select adder (A1CSA) is replaced by the proposed A1CSAS in order to the reduce the delay, and time complexity and to improve the speed. A1CSAS is better than A1CSA in terms of LUT's and Delay. The main aim of the project is to maintain a simplicity construction and reduce LUT's and Delay. The simulation results are obtained by using Xilinx ISE 14.5 version tool.

Design and Simulation of Single-Precision Inexact Floating-Point Adder/Subtractor

Vol. 6  Issue 4
Year: 2016
Issue:Jun-Aug 
Title:Design and Simulation of Single-Precision Inexact Floating-Point Adder/Subtractor
Author Name:B. Venkata Vinod Kumar and Sk. Mahaboob Basha
Synopsis:

To represent very large or small numbers, a wide range of fixed point representation is required, which is no longer effective. These numbers can be represented based on the IEEE-754 standard. This paper presents the designing of an inexact floating-point adder/subtractor which can perform addition, and subtraction operations. These operations are performed based on the single-precision floating-point format that uses IEEE754-2008 standard. An inexact circuit offers an approach that reduces both static and dynamic power for error tolerant applications. The normalization and rounding operations are the related operations, which are dealt with in terms of inexact computing. The main objective of this design is to decrease the area and increase the speed. The results of this inexact floating-point unit are below 30% error deviation, which is acceptable. The inexact floating point Adder/subtractor is modeled in VHDL and the simulation results are obtained from Xilinx ISE 14.5.

A Novel Low Voltage, Full-Swing Voltage-Controlled Oscillator Based on Single-Ended Delay Cell

Vol. 6  Issue 4
Year: 2016
Issue:Jun-Aug 
Title:A Novel Low Voltage, Full-Swing Voltage-Controlled Oscillator Based on Single-Ended Delay Cell
Author Name:Syed Fayaji, T. Krishna Murthy and K. Neelima
Synopsis:

The conventional Voltage-Controlled Oscillators (VCO) are impractical to generate the full swing outputs and wide range of tuning, because the conventional differential VCO's are used as the tail current sources. The full swing, wider tuning range and low voltage VCO's are widely used in every applications. This paper proposes a new CMOS VCO. The proposed VCO uses a single-ended delay cell and achieves the widest tuning range, speed in operation and improved noise performance. The supply voltage used in the proposed system is 1.2V. Moreover, it's simple topology features multiple advantages like area and linear frequency-voltage characteristics. The proposed system has achieved a very wide range of tuning and good noise performance compared to the conventional VCO's. The topology can be used in pulse based applications.

Active Inductance based Relaxation Oscillator for 2.41GHz ISM Receivers

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:Active Inductance based Relaxation Oscillator for 2.41GHz ISM Receivers
Author Name:K. Venkatesh and T. Ravi Sekhar 
Synopsis:

An embedded active inductance technique is used in 2.41GHz ISM Receiver IQ VCO-mixer. The receiver consists of an active inductance topology and the VCO-mixer network, which is designed for low area and low power. The VCO-mixer is based on an IQ cross-coupled embedded active inductor VCO, where the two single oscillators are coupled through active loads. RC oscillators have the advantage of being inductorless (i.e. low area), while typically having a high power consumption. As for quadrature, the coupling of two single oscillators is done with a shunt technique that uses PMOS as active loads, instead of the resistors. The mixer is an add-on to this oscillator, taking advantage of its similarities with a single-balanced mixer. The use of the active load increases the conversion gain. This topology consumes approximately 11.4 % less power in comparison to the IQ cross-coupled RC relaxation VCO-mixer. The mixing function is incorporated in the IQ VCO, benefiting from an increased gain. The receiver IQ VCO-mixer has a gain of 12.22 dB and a noise figure of 7.98 dB, consuming 7.98 mW from a 1.2 V power supply.

CMOS Dual Loop PLL with Improved Noise Performance and Reduced Power Dissipation

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:CMOS Dual Loop PLL with Improved Noise Performance and Reduced Power Dissipation
Author Name:N. Lakshmi Narayana and K. Neelima
Synopsis:

In this paper, a Dual Loop PLL has been designed. In the proposed design, a DL-PLL is designed in two ways. The first method is, that the two PLLs are connected to a mixer and in the second method, the two PLLs are directly cascaded. The two designs will give better results, when compared with the normal CP-PLL. The proposed DL-PLL consists of an AND based PFD and a CP circuit with switching scheme, such that the proposed PFD eliminates the missing edge and phase ambiguity problems in the conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and the charge injection error problem with this new design technique. By using the normal CP-PLL, the total noise performance will be -91.134 dB/Hz and the power dissipation will be 357831.4 mW. By using the DL-PLL with a mixer, the power dissipation will be reduced to 4.2005 mW, but the total noise performance will be somewhat good. By using the second type of DL-PLL that is by directly cascading two PLLs, the power dissipation is reduced to 2.581 mW and the total noise performance will be -133.93 dBc/Hz at 100 MHz offset frequency for a load capacitance of 0.01 μF. The current noise of the PFD and CP circuit has been measured from the transistor level simulation to find the phase noise of the Dual Loop PLL, for output frequency of 2.4 GHz with 100 MHz reference signal in Hspice (Hspui) using awan waves and HSPICE RF Tool. The proposed Dual Loop PLL will have an improved noise performance of -42 dB when compared to the existing charge pump PLL circuits. In addition, the total noise and power dissipation modeling has been done to find the output total noise and Power dissipation of the PLL, considering the PFD and CP output current noise measured at the transistor level in 0.18 μm CMOS.

A Modified Partial Product Generator for Binary Multipliers using Different Adders

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:A Modified Partial Product Generator for Binary Multipliers using Different Adders
Author Name:A. Divya Teja, K. Charan Kumar and K. Neelima 
Synopsis:

Digital multipliers are widely used in the arithmetic units of microprocessors, multimedia and digital signal processors. The main aim of this research work is to design high performance multipliers using different radix to different adders. Modified booth encoding technique is used in this proposed design, where extra partial products are reduced to half. Therefore, the accumulation stages are reduced. By this design, it significantly improves speed, area and delay which is a main objective and purpose of the study. Modified booth encoding technique improves the power delay product by using different types of adders with different radix such as radix-4, radix-8, and radix-16. The used adders are ripple carry adder and carry look-ahead adder, where these are used to know the exact difference by their comparison in terms of delay and area by using Xilinx ISE 14.5 tool with high performance parameters.

Wideband Band Pass Filter with Open Stubs using Quadruple Mode Ring Resonator

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:Wideband Band Pass Filter with Open Stubs using Quadruple Mode Ring Resonator
Author Name:Mohammad Mujahid, G. D. Bharti and B. S. Rai 
Synopsis:

In this paper, a compact wideband Band pass filter has been designed. Quadruple resonance modes are generated by using the inter digital coupled lines and multimode resonator to achieve a wideband. By adding stubs with multimode ring resonator, an extra transmission poles is introduced at 3.5GHz. By introduction of transmission zero at 5.8 Ghz, a good stop band performance is achieved. Designed Bandpass filter is well suited for WLAN at 2.45 and 5.2 GHz. A wide pass band is achieved from 2.45 GHz to 5.2 GHz providing 3 dB Bandwidth of 2.75 GHz and 3 dB Fractional Bandwidth of 71.8%. Good insertion loss nearly about 1.7 dB and return loss more than 15 dB are achieved with high selectivity at both sides of pass band. Designed filter is simulated using the commercially available simulation tool, HFSS.

Design and Analysis of 32x32 Bit ALU using High-Speed Vedic-Wallace Multiplier Based on Vedic Mathematics

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:Design and Analysis of 32x32 Bit ALU using High-Speed Vedic-Wallace Multiplier Based on Vedic Mathematics
Author Name:Kondu Dharitha Reddy and P. V. Mahesh 
Synopsis:

This paper is devoted to design a high-speed Arithmetic Logic Unit. All of us know that, ALU is a module which can perform arithmetic and logic operations. The speed of ALU greatly depends upon the speed of the Multiplier. This paper presents a technique called, “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. Here, a high-speed 32x32 bit multiplier is designed and analyzed which is based on the Vedic mathematics mechanism. The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics. The internal multiplier is implemented using Vedic-Wallace structure for high-speed implementation. The exponent of the final result is obtained by using Brent-Kung adder for fast computations with less area utilization. The projected Vedic multiplier is coded in a High-level Digital Language (VHDL) followed by synthesization using an EDA tool, XilinxISE14.5. The proposed ALU is able to perform three different arithmetic and eight different logical operations at high speed. The main objective of this paper is to increase the speed of the multiplier and to decrease the delay, and area of the hardware.

Performance Comparison of LMS, NLMS, RLS Adaptive Filtering Techniques

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:Performance Comparison of LMS, NLMS, RLS Adaptive Filtering Techniques
Author Name:M. Koteswara Rao and I. Santhi Prabha 
Synopsis:

This paper gives information about the comparison of adaptive filtering techniques like fixed LMS, Normalized Least Mean Square, and RLS for noise elimination in speech communication systems. The main objective of this paper is to suppress the additive noise which is due to the effect of environmental conditions in the communication systems. In these days, additive noise is one of the major problems in the communication, especially in the digital electronic circuit design. The origins of additive noise are because of atmospheric conditions, weather situations around the system and any other disturbances. Generally, the coefficients of filter updation in a basic filter does not occur time to time, as it may affect the desired information. By updating the coefficients of the filter time to time, this problem could be eradicated and thereby increasing the number of iterations for the filtering process, which gives efficient results. In the communication systems, the performance of these adaptive filters are in terms of mean square error, signal to noise ratio, rate of convergence, etc. In this research paper, the authors have discussed about how to cancel out the additive noise which is combined to the input speech signals that observes the records of signal to noise ratio, and mean square error. Finally, this article compares those results experimentally with the help of MATLAB programming and calculation tool. The mean square error improvement with the number of iterations for different noise signals are represented graphically. By the observation of the graphical results, the rate of convergence and reception level for the given speech and noise signals were found.

A Novel Multilevel Inverter with Minimum Switches

Vol. 6  Issue 2
Year: 2016
Issue:Dec-Feb 
Title:A Novel Multilevel Inverter with Minimum Switches
Author Name:Manjunatha B.M., Ashok Kumar D.V. and Vijay Kumar M.
Synopsis:

This paper presents an unique three phase seven level inverter with reduced number of switches. Multilevel Inverters (MLI) are used in high power and high voltage applications as they are capable of producing multiple levels in output voltage with reduced THD. To reduce THD further, the number of levels in the output voltage has to be increased, which is directly associated with the number of switches required. To accomplish this, the conventional MLI experiences complexity in control, number of required DC sources, size, switching losses and cost of overall system increases. The proposed topology overcomes the aforesaid limitations and compared with the conventional MLI in terms of the number of switches, DC sources, capacitors, fundamental voltage, and THD. The performance is analyzed by using a simulation tool.

Comparative Analysis and FPGA Implementation of Vedic and Booth Multiplier

Vol. 6  Issue 2
Year: 2016
Issue:Dec-Feb 
Title:Comparative Analysis and FPGA Implementation of Vedic and Booth Multiplier
Author Name:Parul Agrawal and Rahul Sinha
Synopsis:

The digital computing systems like mathematical co-processors, micro-processors, digital filters must be highly efficient in terms of computational time. The most fundamental operation in any computing systems is multiplication. The multiplier should therefore employ minimum processing time by the use of high speed adders. This paper describes the design of Vedic Multiplier using Kogge Stone Adder (the fastest Parallel Prefix Adder) and Booth Multiplier (based on two's complement notation). The two designs have been compared based on delay, levels of logic, number of slices, and memory usage. Based on the synthesis report obtained, the delay in Booth Multiplier has been found to be very less compared to Vedic Multiplier however, during simulation in Booth Multiplier the response to the inputs is not instantaneous, but there is a large amount of wait period in getting the output as the count signal increments in the sequential circuit which is not the case with Vedic Multiplier (Combinational Circuit). This showed that the Booth Multiplier is slower compared to Vedic Multiplier. The two designs have been implemented in Xilinx ISE 14.4 for the family of devices Spartan 6 with the device name Xc6slx45, package csg324,and speed grade of -3.

Voltage Mode Second Order Notch/All - Pass Filter Realization Using OTRA

Vol. 6  Issue 2
Year: 2016
Issue:Dec-Feb 
Title:Voltage Mode Second Order Notch/All - Pass Filter Realization Using OTRA
Author Name:Rashika Anurag, Neeta Pandey, Rohan Chandra and Rajeshwari Pandey
Synopsis:

This paper presents a Second Order Notch/All pass filter based on Operational Transresistance Amplifier (OTRA). It uses two OTRA's and five resistances. To add electronic tunability, the filter uses a capacitor array that can be controlled by switches. The switches are also used to provide inverting and non inverting Notch/All pass as response. This adds flexibility in phase response of all pass filter. The notch/all pass configuration is a modified extension of the Delyiannis-Friend circuit. Through the addition of a second active block which basically acts as a summer for the input voltage and the output of the first OTRA block. The functionality of the proposed filters is verified through SPICE simulations using CMOS based implementation of OTRA. The power supply for the implementation is 1.5V and is based on 0.5 submicron technology.

Trichotomous Visual Analytics [TVA]: Visual Statistical Cumulative Data Analysis via the Tri–Squared Calculator A Digital Instrument Designed to Present the Outcomes of the Tri–Squared Test

Vol. 6  Issue 2
Year: 2016
Issue:Dec-Feb 
Title:Trichotomous Visual Analytics [TVA]: Visual Statistical Cumulative Data Analysis via the Tri–Squared Calculator A Digital Instrument Designed to Present the Outcomes of the Tri–Squared Test
Author Name:James Edward Osler II
Synopsis:

This paper presents an innovative digital instrument the Tri–Squared Calculator © that uses the novel Trichotomous Visual Analytics [TVA] as a supportive research model for traditional confirmatory trichotomous statistical analyses. This research adds to the publication entitled, “Trichotomous Exploratory Data Analysis [Tri–EDA]: A Post Hoc Visual Statistical Cumulative Data Analysis Instrument Designed to Present the Outcomes of Trichotomous Investigative Models” published in the imanager's Journal on Instrumentation and Control Engineering. This narrative provides an epistemological rational for the use of “Trichotomous Exploratory Data Analysis” and other trichotomous statistical analytical models for the in–depth analysis of the transformative process of qualitative data into quantitative outcomes through the Tri–Squared Test. The Tri–Squared Test was first introduced in the i-manager’s Journal on Mathematics, and further detailed in the Journal on Educational Technology, Journal on School Educational Technology, and in Journal on Educational Psychology. TVA is used in Tri–Exploratory Data Analysis as a series of graphical and visual statistical models that are a part of the Tri–Squared Calculator ©. The Tri–Squared Calculator © digital instrument was created, designed, and developed by the author to quickly calculate and report Tri–Squared Test outcomes. It also allows the researcher to rapidly check the validity and reliability of Tri–Squared Test results. This is a novel approach to advanced statistical Tri–Squared modeling and reporting. It adds a potent new tool to the mixed methods approach of the trichotomous research design (that intrinsically involves the holistic trichotomous combination and comparison of qualitative and quantitative data outcomes).

RFID Technology for Biomedical Applications: State of Art and Future Developments

Vol. 6  Issue 2
Year: 2016
Issue:Dec-Feb 
Title:RFID Technology for Biomedical Applications: State of Art and Future Developments
Author Name:Roberto Marani and Anna Gina Perri
Synopsis:

In this paper some of the possible applications in the biomedical field of the RFID technology are presented, giving an idea of the wide range of advantages that RFID devices are able to provide. In particular, those aspects of RFID technology were examined, which make possible the realization of miniaturized devices, implantable in the human body and powered from the outside, and can monitor the biological functions of individuals or even enable the therapy of diseases. Moreover, some aspects that need to be improved in the future research works are discussed such as the biocompatibility of the material for the implantable devices, the long-term exposure of the human body to electromagnetic fields, the interference caused by surrounding metallic parts, the attenuation of RF signals at particularly high frequency values and the implementation of a safe communication channel in order to guarantee the privacy of the individual.

Study of Electromagnetic Interference

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title:Study of Electromagnetic Interference
Author Name:M. Satish Kumar and A. Jhansi Rani 
Synopsis:

The life on Earth has been adapted to survive in an environment of natural low-frequency Electromagnetic (EM) fields in addition to the Earth's Static Geo-Magnetic field. Natural EM fields of low frequency come from two main sources, the sun and thunderstorm activity. However, fields produced by various Electrical and Electronic Systems such as Radio and Television broadcast stations, Communication Transmitters etc., and Automobile Ignition systems, Industrial Control Equipment radiate Electromagnetic Energy at much higher intensities during their normal operation. The electromagnetic environment created by these Intentional and Unintentional sources with a very different Spectral Distribution has altered this natural EM background. The electromagnetic environment created by these Intentional and Unintentional sources, when sufficiently strong, Interferes with the operation of many electrical and electronics equipment and systems which degrades the performance of the system. So the study of Electromagnetic Fields which becomes an interference to the Systems’ operation is needed. For analysis of EM fields, simulation of Co-Axial cable using CST is considered [4].

A Novel Method to Eliminate Selective Harmonics in a Multilevel Inverter

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: A Novel Method to Eliminate Selective Harmonics in a Multilevel Inverter
Author Name:Nimain Charan Nayak
Synopsis:

This paper deals with the harmonic elimination in multilevel inverters. Multilevel inverters are advanced types of inverters. The desired level of levels is obtained by using the method of triggering. A seven level cascaded H-bridge inverter has been used here. To synthesize multilevel output AC voltage using different levels of DC input, semiconductor devices must be switched on and off. The output contains harmonic and total harmonic distortion. These affect the solution and hence have to be eliminated. Selective harmonic elimination is the method in which the author selects the harmonics which needs to be eliminated. Different methods are used to eliminate the harmonics. In this paper, the author makes use of genetic algorithm to eliminate the harmonics. Genetic algorithm is a computational algorithm that solves optimization problem by imitating the genetic processes and the theory of evolution. It imitates biological evolution by using parameters such as reproduction, crossover mutation etc. The fitness function of multilevel inverters is solved and firing angles are obtained. These firing angles are obtained to the semiconductor devices and output with minimum harmonics and total harmonic distortions are obtained.

OTRA Based Precision Rectifier

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: OTRA Based Precision Rectifier
Author Name:Rashika Anurag, Neeta Pandey, Rajeshwari Pandey, and Ritu Vijay
Synopsis:

Analog integrated circuit design is receiving a tremendous boost due to the development and application of Current- Mode (CM) processing. Application of CM techniques provides wider bandwidth; which is virtually independent of the closed loop gain, greater linearity and large dynamic range. The Operational Transresistance Amplifier (OTRA) has emerged as an effective alternate current mode analog building block. It is a high gain current input, voltage output amplifier and also free from parasitic input capacitances and resistances as its input terminals are virtually grounded thus eliminating response limitations due to parasitics. OTRA is used as an analog building block for realizing a number of circuits having applications in signal processing and generation. Precise rectification is an important requirement in instrumentation and measurement circuits and is addressed in this paper. Traditionally, diodes are used to build rectifiers however; rectification is not permitted below a voltage of ∼ 0.7 V for silicon and ∼ 0.3 V for germanium diodes due to cutin voltage. For low voltage applications, Operational Amplifiers (OPAMP) with diode connected in feedback is used which prevents the fast switching of the diodes in high frequency range due to slew rate limitation of OPAMP. This paper aims at presenting an OTRA based FWR which is suitable for low voltage rectification. The functionality of the proposed circuit is validated through SPICE simulation for which OTRA is realized using Current Feedback Operational Amplifier (CFOA).The simulation results are found in close agreement to the theoretical results.

Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop
Author Name:S. Suvarna, K. Rajesh, and S. Veerakumar
Synopsis:

Digital multipliers are most efficiently used in many applications such as Fourier Transform, Discrete Cosine Transforms, and Digital Filtering for high speed and low power consumption. The throughput of the multipliers is based on speed of the multiplier, and if it is too slow then, the entire performance of the circuit will be diminished. The pMOS transistor in negative bias cause Negative Bias Temperature Instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause Positive Bias Temperature Instability (PBTI). These effects reduce the transistor speed and the system may fail due to timing violations. So here, a new multiplier was designed with novel Adaptive Hold Logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), it is possible to reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

Trichotomous Bayes Factor Analysis [Tri–BFA]: A Post Hoc Probability Confirmatory Data Analysis Assurance Model Designed to Determine the Validity, Viability, and Verifiability of E–Learning Hypotheses

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: Trichotomous Bayes Factor Analysis [Tri–BFA]: A Post Hoc Probability Confirmatory Data Analysis Assurance Model Designed to Determine the Validity, Viability, and Verifiability of E–Learning Hypotheses
Author Name:James Edward Osler
Synopsis:

This paper presents meticulous knowledge about ‘Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content for Electronics and Digital Learning Ecosystems’. This narrative provides an epistemological rational for the use of Bayesian probability statistical testing models for E–Learning via the Tri–Squared Test and subsequent TRINOVA Post Hoc test methodology. TRINOVA is an in–depth [Trichotomous Nomographical Variance] statistical procedure for the internal testing of the transformative process of qualitative data into quantitative outcomes through the Tri–Squared Test. Tri–Bayes Factor Analysis (or “Tri–BFA”) is an advanced statistical measure that is designed to check the validity and reliability of a Tri–Squared Test hypothesis using Bayesian probability. This is a novel approach to advanced statistical post hoc Tri–Squared hypothesis testing. It adds merit and considerable value to the mixed methods approach of research design that involves the holistic combination and comparison of qualitative and quantitative data outcomes. A sequential series of steps using the Tri–Squared Test, TRINOVA, and Tri–BFA mathematical models are provided to illustrate the entire process of advanced statistical Trichotomous inquiry.

Simulation Analysis and Design of an Optimized Controller Model for Photovoltaic System Under Uniform and Non-Uniform Shaded Conditions

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Simulation Analysis and Design of an Optimized Controller Model for Photovoltaic System Under Uniform and Non-Uniform Shaded Conditions
Author Name:Kakarla Deepti, P. Srihari and K. Manjunathachari
Synopsis:

The manufacturing and utilization of photovoltaic arrays have advanced dramatically in the recent years. The use of new, efficient Photovoltaic Solar Cells (PVSCs) has emerged as an alternative measure of renewable green power, energy conservation and demand side management. Maximum Power Point Tracking (MPPT) techniques are employed in photovoltaic (PV) systems to make full utilization of PV array output which depends on solar irradiation and temperature. These techniques vary in many aspects as range of effectiveness, hardware, sensor required and cost. This paper presents an optimized controller design which increases the conversion efficiency of a photovoltaic system under variable temperature and irradiance conditions. It also includes the comparison of the efficiency of the PV system by incorporating the controller circuit on the existing MPPT algorithms in real time and in simulation. Different development stages are presented and then the optimized controller is simulated and evaluated which has shown better performances. Matlab Simulink tools have been used for performance evaluation on energy point. Simulation will consider different solar irradiance and temperature variations. The real time model produced includes rotating the panel under uniform and non uniform shaded conditions which is driven by a brush motor.

Voltage Mode Universal First Order Filter Employing Single OTRA

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Voltage Mode Universal First Order Filter Employing Single OTRA
Author Name:Honey Gahlawat, Hemant Kumar, Jatin Kamnani, Gaurav Dagar and Rajeshwari Pandey 
Synopsis:

Mixed mode circuit design is the current trend in VLSI industry, where both analog and digital circuitry can be fabricated using standard digital CMOS technologies. However, these technologies do not lend themselves to analog design, requirting novel circuit design techniques that are compatible with standard CMOS processes. Consequently, over the last few decades Current-Mode (CM) processing has evolved as a novel design technique which has resulted in emergence of numerous analog building blocks. The operational transresistance amplifier (OTRA) is one among those. It is a high gain current input voltage output device which provides the advantages of current mode design techniques and can readily be used for voltage-mode applications.

This paper presents a new voltage mode Multi-Input Single Output (MISO) first order universal filter using single OTRA. The presented topology can be used to realize low-pass, high-pass and all-pass filter functions through appropriate input selections. The configuration is made fully integrated by implementing the resistors using matched transistors thereby reducing chip area. The proposed circuit is insensitive to parasitic capacitances and resistances due to internally grounded input terminals of OTRA. The effect of non-ideality of OTRA on the proposed circuit is also analysed. Functionality of the proposed configuration is verified through PSPICE simulations using 0.5 μm CMOS process parameters. The simulation results are in tune with the theoretical propositions.

Study of HEMTs Thermal Parameters Based on I-V Characteristics Analysis

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Study of HEMTs Thermal Parameters Based on I-V Characteristics Analysis
Author Name:Leonardo Suriano, Roberto Marani and Anna Gina Perri
Synopsis:
This paper presents a light DC thermal model of recessed gate P-HEMT devices, based on the Chaibi model, where the authors have identified the transistor parameters having greater influence on the device behaviour for temperature variations. The main aims are to improve the accuracy of modelled I-V curves, in particular in the knee and saturation regions and above all to give the device source-drain current as a function of external voltages, as seen at the device gates, by-passing the very difficult measurement of parasitic resistances for the I-V characterisation. To verify the accuracy of the proposed model, the results are compared with those of Chaibi model, obtaining a negligible relative error, with however a compilation time and a run time much more low.

Introducing Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content For Electronics and Digital Learning Ecosystems

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Introducing Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content For Electronics and Digital Learning Ecosystems
Author Name:James Edward Osler II 
Synopsis:
This monograph provides an epistemological rational for the novel “Tri–Factor Analysis” statistical model and metric. This new statistic is an innovative and in–depth way of investigating the overall effectiveness of teaching and learning in digital learning environments and Ecosystems. Tri–Factor Analysis is grounded in the Eduscience (Osler, 2013a) Tri–Factors of: Performance, Efficacy, and Content. Along with the Tri–Squared Test (first introduced in the Journal on Mathematics) it is a mathematically–grounded analytical methodology designed to provide educators with quantitative tools, metrics, and analytics that aid in pedagogical (and andragogical) investigation. The use of the Tri–Factor Analysis methodology also adds value to educational inquiry that has been formatted as an eduscientifically–engineered research design that involves the critical analysis of overall classroom and individual learning in digital learning Ecosystems.