Vol. 5 Issue 2
Year: 2015
Issue: Dec-Feb
Title: VLSI Modeling Of FM0/Manchester Encoder Using EDML Technique For DSRC Application Systems
Author Name: P. Lokesh, V. Thrimurthulu and L. Mihira Priya
Synopsis:
The aim of this paper is to promote intelligent road and vehicle safety systems in order to control the accident rates and vehicle damages by using Dedicated Short Range Communication (DSRC). The DSRC is of two types: automobile-toautomobile and automobile-to-roadside. In automobile-to-automobile, the DSRC has the ability of message sending and broadcasting among automobiles for safety issues and public information announcement. In this paper, the authors propose a complete simulation model of Dual Mode Logic, (DML) Technique. This method increases the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings being used for the Dedicated Short- Range Communication (DSRC) which is a budding technique to drive the smart transportation system into our daily life with low power digital system designs. The maximum operating frequency is 7GHz and 4GHz for Manchester and FM0 encoding. The on board power consumption is 1133 mW at 3.352 V for Manchester encoding and 1106 mW at 3.352 V for FM0 encoding. The presentation of this paper is evaluates 32nm CMOS technology by utilizing the design simulation Xilinx Vivado tools and layout simulation with extended DML Techniques using Microwind simulator. This paper not only provides a fully reused architecture but also exhibits high performance.
Year: 2015
Issue: Dec-Feb
Title: VLSI Modeling Of FM0/Manchester Encoder Using EDML Technique For DSRC Application Systems
Author Name: P. Lokesh, V. Thrimurthulu and L. Mihira Priya
Synopsis:
The aim of this paper is to promote intelligent road and vehicle safety systems in order to control the accident rates and vehicle damages by using Dedicated Short Range Communication (DSRC). The DSRC is of two types: automobile-toautomobile and automobile-to-roadside. In automobile-to-automobile, the DSRC has the ability of message sending and broadcasting among automobiles for safety issues and public information announcement. In this paper, the authors propose a complete simulation model of Dual Mode Logic, (DML) Technique. This method increases the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings being used for the Dedicated Short- Range Communication (DSRC) which is a budding technique to drive the smart transportation system into our daily life with low power digital system designs. The maximum operating frequency is 7GHz and 4GHz for Manchester and FM0 encoding. The on board power consumption is 1133 mW at 3.352 V for Manchester encoding and 1106 mW at 3.352 V for FM0 encoding. The presentation of this paper is evaluates 32nm CMOS technology by utilizing the design simulation Xilinx Vivado tools and layout simulation with extended DML Techniques using Microwind simulator. This paper not only provides a fully reused architecture but also exhibits high performance.
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