Effective Low Power And High Performance Of Multimodulus Prescaler

Vol.4  No.3

Year: 2014

Issue: Mar-May

Title : Effective Low Power And High Performance Of Multimodulus Prescaler

Author Name : Silambarasan A Silambarasan, DINESH KUMAR

Synopsis :

The high speed dual modulus prescaler is one of the important functional blocks in frequency synthesizers. The dual modulus prescaler design is the bottleneck of the synthesizer, as it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) normally consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. Usually, dual modulus prescaler consists of Flip flops and some extra logic implemented using logic gates which determine the terminal count. Here an E-TSPC [Extended True Single Phase Clock] logic based divide-by-2/3 prescaler using pass transistor logic is suitable for low supply voltage (0.9V) and low power applications have been designed and implemented. Here the counting logic and the mode selection control are implemented using a single P-MOS transistor. Thus the critical path is reduced and also increases its working frequency. Simulation results show that, compared with the conventional TSPC [True Single Phase Clock] and E-TSPC based 2/3 prescaler designs as much as 46% in PDP, 24% in operation speed and 44% in area can be achieved by the proposed design. Also the proposed 2/3 prescaler are designed and implemented to design a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler. The power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler designs shown by the simulation results.

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Design of Ripple Carry Adder Using Constant Delay Logic

Vol.4  No.3

Year: 2014

Issue: Mar-May

Title : Design of Ripple Carry Adder Using Constant Delay Logic

Author Name : kathiresan R, THANGAVEL

Synopsis :

In this paper, Wallace tree multiplier using the constant delay logic style and less number of transistors were designed and analyzed. Constant Delay (CD) logic provides low power consumption and to adjust the window width of the clock pulse, CD logic produces quick output evaluation before the input arrival for operation. Using these features, performance is good compared to normal static and dynamic logic. In this design, the timing block and logic block are implemented to reduce the static power dissipation and also to reduce the unwanted glitch in the output. This experimental result shows smaller power consumption and reduced chip area compared to the existing design.

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Low Power dissipation of Ring Counter using Dual sleep Transistor approach

Vol.4  No.3

Year: 2014

Issue: Mar-May

Title : Low Power dissipation of Ring Counter using Dual sleep Transistor approach

Author Name : Balaji Morasa, KEERTHANA , VARUN K

Synopsis :

In CMOS [Complementary Metal Oxide Semiconductor] integrated circuits design, scaling is challenged by higher power consumption. The significant growth in power dissipation has occurred mainly due to the higher clock speeds in addition to the smaller process geometries. The transistor packaging density and functionality on a chip is improved by scaling. The speed and frequency of operation is increased due to scaling and hence higher performance is achieved. When the technology scales down, then the leakage current increases exponentially. In 90 nm and below technologies, leakage power constitutes 30-40% of total power dissipation. In this paper, a dual sleep transistor approach is used for reducing the power dissipation of ring counter circuit with minimum possible area. The simulations were done using Micro wind Layout Editor and DSCH [Digital Schematic Editor] software.

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Efficient Implementation Of Gate Oxide With And Without Breakdown In SRAM – BISR For Word Oriented Memories

Vol.4  No.3

Year: 2014

Issue: Mar-May

Title : Efficient Implementation Of Gate Oxide With And Without Breakdown In SRAM – BISR For Word Oriented Memories

Author Name : Devi priya, S.LAVANYA , ASWIN TILAK.A

Synopsis :

Scaling of the CMOS [Complementary Metal Oxide Semiconductor] technology associated with gate oxide thickness has become a major barrier for the design of circuit in nanoscale Static Random Access Memory (SRAM), especially in lower voltages. The operation of SRAM arrays are critical in reducing the power consumption. The Gate Oxide Breakdown caused by excessive electric field in the gate oxide causes increased vulnerability of the circuit performance, during breakdown. The devices are characterized by increased minimum voltage due to increase the static write failure as the voltage decreases. The design circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Micro wind 2 VLSI layout CAD tool. The proposed structures are simulated using Xilinx ISE design suite.

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QCA Based Low Power Parallel Binary Adder/Subtractor Using Reversible Logic Gates

Vol.4  No.3

Year: 2014

Issue: Mar-May

Title : QCA Based Low Power Parallel Binary Adder/Subtractor Using Reversible Logic Gates

Author Name : sasikala Govindhasamy, Maragatharaj

Synopsis:

Quantum Dot Cellular Automata (QCA) is an emerging nanotechnology in the field of Quantum electronics for low power consumption and high speed of operational phenomenon. Such type of circuit can be used in many digital applications where CMOS [Complementary Metal Oxide Semiconductor] circuits cannot be used due to high leakage and low switching speed. Also, reversible logic is becoming a more and more prominent technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. Reversibility plays an important role when energy efficient computations are considered. By combining both of these low power and area efficient QCA technologies, the author can make a new generation low power system. In this paper, reversible eight-bit parallel binary adder/Subtractor using QCA has been proposed. This method reduces the total area used compared to the normal CMOS based structures and reduces power dissipation by using reversible logic gates.

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Modified Divide by 2/3 Counter Design Using MTCMOS Techniques

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Modified Divide by 2/3 Counter Design Using MTCMOS Techniques

Author Name : Tamilmani R, Rajesh.K , Santhiyakumari N

Synopsis :

In this paper, the leakage power and speed performances of extended-true single phase clock and MTCMOS using true single phase clock prescaler are investigated. Based upon this study, MTCMOS technique is implemented in true single phase clock logic DFF design. By using a wired OR logic, only one transistor is used for both mode selection and counting logic system. The working frequency of the counter is enhanced and reduced the critical path between the DFF. Using MTCMOS technique a static leakage power is reduced and the speed performances are improved. The designed counter is compared in term of power consumption using DSCH and Micro wind tools.

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Design Of Energy Constrained Turbo Architecture

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Design Of Energy Constrained Turbo Architecture

Author Name : Sabarinatha Prabhu, Gomathi , Santhiyakumari N

Synopsis :

Wireless Sensor Network can be considered to be energy constrained wireless scenarios, since the sensors are operated for extended periods of time, while relying on batteries that are small, lightweight and inexpensive. Energy constrained wireless application is done with the help of Lookup Table-log-BCJR (LUT-Log-BCJR) architecture. In our existing system the conventional LUT-Log-BCJR architecture have wasteful designs requiring high chip areas and hence high energy consumptions Energy constrained applications. This motivated our proposed System the LUT log BCJR is designed with Clock gating technique achieves low-complexity energy-efficient architecture, which achieves a low area and hence a low energy consumption, and also achieving a low energy consumption has a higher priority than having a high throughput. we use most fundamental Add Compare Select (ACS) operations and It having low processing steps, so that low transmission energy consumption is required and also reduces the overall energy consumption.

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High Resolution Display Systems Using Current-Steering DAC

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : High Resolution Display Systems Using Current-Steering DAC

Author Name : Rekha Rekha P, N. Vijayanandam N. Vijayanandam

Synopsis :

This paper focusses on foreground calibration technique. For high speed and high resolution video applications, current steering DAC is preferred. In the large current sources, linearity error is introduced and detected by using two current tunning loops and digital controller. In this paper, Vcm based switching method injected between MUX and DAC to compensate the error which reduces the time of operation. For 12-bit DAC prototype realized 90nm CMOS process,90% gate area reduction current source array is achieved. The measurement result demonstrates that the calibrated converter achieves both DNL and INL less than 1LSB.

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Accumulator Based Test Pattern Generation Of Multiple Single Input Change Vectors

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Accumulator Based Test Pattern Generation Of Multiple Single Input Change Vectors

Author Name : jayadevi S, Santhiyakumari N

Synopsis :

This paper discusses about an efficient Test Pattern Generator (TPG) for built-in self-test. This method generates Multiple Single Input Change (MSIC) vectors in a pattern.A reconfigurable Johnson counter and an accumulator is combined to generate a class of minimum transition sequences. The TPG used in this paper is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also explained to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results shows that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are used. Simulation results with ISCAS benchmarks demonstrates that MSIC can save test power and impose no more than 10% overhead for a scan design. It also achieves the target fault coverage without increasing the test length, and also saves power up to 50%.

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Simulation of QCA Based Binary to BCD Converter in Xilinx using HDLQ

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Simulation of QCA Based Binary to BCD Converter in Xilinx using HDLQ

Author Name : sasikala Govindhasamy, Maragatharaj

Synopsis :

Quantum Dot Cellular Automata (QCA) is an emerging nanotechnology in the field of Quantum electronics for the low power consumption and high speed of operational phenomenon. Such type of circuit can be used in many digital applications where CMOS circuits cannot be used due to high leakage and low switching speed. The code converters are the basic units for conversion of data to perform arithmetic operations. A new effective binary to BCD converter design using QuantumDot Cellular Automata is presented in this paper. Compared to the available code converters in VLSI technology, this method of using Quantum dots reduces area and increases switching speed. 3-input Majority gate is the basic and universal gate in QCA design. In accordance with the code converter design using 3-input majority gate logic, a 5-input majority gate logic structure is also used here to design the binary to gray code converter. This replacement improves the speed of the system by reducing number of clock cycles required to produce the output. The simulations are done using Xilinx ISE Design suite to get power and timing analysis.

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