An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms
Author Name: Charan Kumar K and Sunil Kumar K
Synopsis:
This paper presents the design and comparison of the high speed single precision binary floating point multiplier using IEEE-754 format implemented through the Faster Dadda, Vedic from Dadda and the modified Booth algorithm. The Faster Dadda algorithm utilizes the parallel independent column compression technique and the Hybrid adder. The Vedic from Dadda is the concept of utilizing the Dadda to get higher order multiplier through Vedic concept. Integer multiplication can be inefficient and costly, in time and hardware, depending on the representation of signed numbers. The modified Booth algorithm uses the encoding techniques which minimize the partial products. These single precision Floating point multipliers based on IEEE 754 are implemented using VHDL and they are targeted for Xilinx Spartan-3E FPGA. The performances of these multipliers are analysed in terms of speed, area and area-delay product.