A Review on Miniaturized Microstrip Technology along with Metamaterial for Low Pass filter application

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: A Review on Miniaturized Microstrip Technology along with Metamaterial for Low Pass filter application
Author Name: Akshay Kumar Srivastava, Arvind Pandey and B.S.Rai 
Synopsis:
This paper provides knowledge about how to decrease the overall physical size and insertion loss of the filter. Metamaterial is taken as a reference to achieve this goal. Physical size and light weight is a major concern in today's integrated circuit. The application of low pass filter is very wide in the field of communication engineering and the complex receiver in which frequency selection is a primary factor and much more. The rate of change of magnitude with respect to frequency (roll off) and the magnitude in pass band are two most important features of any filters. The particular shape of metamaterial having various unit cell has ability to improve the overall performance of filter. This improves selectivity to great extent. Metamaterial in shape of hexagonal-omega structure provides the negative permittivity.

A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application
Author Name: Nitu Rao, Vimal Kumar Mishra and R.K. Chauhan
Synopsis:
In this paper Tunnel Diode Body Contact (TDBC) SOI p-MOSFET with low off-state leakage current is proposed for low power -13 digital application. The device shows off-state current with a drain voltage of 0.5V as about equal to 3.37×10 A -4 9 (33.7pA) and on-state current as about equal to 1.5×10 A (0.15mA) so that on to off-state current ratio is about 10 . This paper also includes the study of different type of SOI MOSFET namely Partially Depleted SOI (PD SOI), Full Depleted SOI (FD SOI) for low power digital application. This paper also includes the comparison between Partially Depleted TDBCS SOI n- MOSFET and proposed TDBC SOI p-MOSFET.

A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles
Author Name: Mareddi Bharathkumar, Palagani Yellappa and D. Revanth 
Synopsis:
In this paper, a novel pliant nanogenerator made of PDMS (polydimethylsiloxane) and ZnO nanoparticles is presented. In this device, ZnO nanoparticles are combined with PDMS to form a nanogenerator. PDMS is a flexible kind of material, which is used to form flexible kind of materials and ZnO is a piezoelectric material which exhibits piezoelectricity. A nanogenerator converts mechanical energy into electrical energy. Mechanical energy refers to energy that we are getting from the surroundings like mechanical pressure, mechanical vibrations, etc. By using this energy we can charge batteries of mobile phones and operate smaller electronic devices through wireless power transmission and also it can give endless power in wireless sensor applications. Now a days people are mainly facing problems with power and low battery power. So, to avoid these problems, energy harvesting is playing a main role in industries. Our work indicates the realization of plaint nanogenerator made of ZnO nanoparticles and PDMS and it has some important and interesting applications in energy harvesting. The applications are mainly for low power electronic devices.

An Efficient Design Of XOR Gate And Its Applications Using QCA

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: An Efficient Design Of XOR Gate And Its Applications Using QCA
Author Name: D. Ajitha , K. Venkata Ramanaiah and V. Sumalatha
Synopsis:
As a substitute for CMOS, innovation of quantum cellular automata was anticipated by Lent et al, to represent exemplary cell automata with quantum dots. Quantum Cellular Automata (QCA) may be a progressive innovation that endeavors the certain nano level issues to perform computing. Its potential advantages are high speed, high device density, and low power dissipation. This paper presents the design of XOR gate with the least number of cells; furthermore the circuit appearance is simple. Exploitation of this novel XOR gate leads to the development of combinational circuits like Half Adder, Full Adder, Parity Generator and Parity Checker etc., which were developed effectively in a single layer structure with less number of cells, area and delay, as compared to the earlier designs. This paper mainly focusses on the construction of optimized combinational circuits without using cross-overs in QCA. Further, the simulation results are presented.

An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms
Author Name: Charan Kumar K and Sunil Kumar K
Synopsis:
This paper presents the design and comparison of the high speed single precision binary floating point multiplier using IEEE-754 format implemented through the Faster Dadda, Vedic from Dadda and the modified Booth algorithm. The Faster Dadda algorithm utilizes the parallel independent column compression technique and the Hybrid adder. The Vedic from Dadda is the concept of utilizing the Dadda to get higher order multiplier through Vedic concept. Integer multiplication can be inefficient and costly, in time and hardware, depending on the representation of signed numbers. The modified Booth algorithm uses the encoding techniques which minimize the partial products. These single precision Floating point multipliers based on IEEE 754 are implemented using VHDL and they are targeted for Xilinx Spartan-3E FPGA. The performances of these multipliers are analysed in terms of speed, area and area-delay product.

Design of FIR Filter for Efficient FPGA Implementation

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: Design of FIR Filter for Efficient FPGA Implementation
Author Name: S.V. Padmajarani and M. Muralidhar
Synopsis:
FIR filters are basic building blocks in Digital Signal Processing applications, require computationally efficient multiply and accumulate operations so the blocks with the desired characteristics have to be chosen carefully. The multiplier is generally slow and occupies large area, the adder also contributes to long delay when the length of the addition is more. Improving the speed results mostly in large areas, usually they conflict with each other. The signal processing applications consume considerable amount of energy. Hence there is a need for low power, high speed, low area circuits for Digital Signal Processing applications. The aim of this paper is to implement a low power, high speed, area efficient FIR filter. Multiply and Accumulate technique is used for multiplier design and the addition and accumulation operations are performed by Parallel Prefix Adders. Some of the available Parallel Prefix Adder architectures and the hybrid architecture of Parallel prefix adder is used here. The implementation is done for 4-tap FIR filter using Xilinx 14.5 version, with the targeted device of Spartan3E FPGA. The experimental results show that the implemented FIR filter using hybrid parallel prefix adder is efficient in area, consume low power and has high speed compared to existing parallel prefix adder models.

Memory Implementation using Multi Bit Flip-Flop

Vol. 5  Issue 2
Year: 2015
Issue: Dec-Feb
Title: Memory Implementation using Multi Bit Flip-Flop
Author Name: Palagani Yellappa, Mareddi Bharathkumar and Shaik Shabana Azmi
Synopsis:
In the digital world memory elements play a vital role. In memory devices the most important factors are Area, Power and Speed. Increased Area and Power consumption of the memory device means reduced device reliability and lifetime. Flip-flops are the basic sequential components used for memory applications. D Flip-flop is one of the most commonly used Flip-flops and delay consumed by clocking is a major part of the whole design. In this paper, the authors analyze the design of Single-Bit Flip-Flop (SBFF i.e. 1-bit) and make a performance comparison over the Multi-Bit Flip-Flop (MBFF i.e. 2-bit, 4-bit, 8-bit, 16-bit and 32-bit). In this paper, the authors design SRAM and DRAM using both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). Designing the memory by using SBFF implies more power consumption. To get the maximum reduction in power and delay an algorithm has been proposed in which SBFFs are replaced with maximum possible MBFF without affecting the performance of the original circuit. These result in favor of Multi-Bit Flip-Flop as reduction of delay such as gate delay and net delay.