Aircraft Asylum Monitoring System Using SPARTAN6 FPGA

Vol. 5  Issue 1
Year: 2014
Issue: Sep-Nov 
Title: Aircraft Asylum Monitoring System Using SPARTAN6 FPGA
Author Name: S. N. Bhuvaneshwari, M. Elakkiyapriya and M. Shenbagapriya
Synopsis:
Aircraft provides a Fast Reliable mode of transport with no comparable alternative for long distance. This paper is used to get the information about the plane, if any accidents or hijack occurs in the plane. The jumbo level sensor used in the plane activates and gives us the digital information about the direction and distance of landing of the plane to the controller. Then the controller allows the signal from the control room to the plane. The TI OMAP in Spartan 6 FPGA used in this paper demonstrates the action in control, the braking, and nose landing gear of the plane. The magnetic sensor also activates, while the controller receives the signal, which deactivates or magnetize the weapons in the plane. This project is mainly used for the aircraft system. It has few advantages with, High safety for plane and passengers, by reducing the plane's hijack and accidents and is easy to find the plane tracking and control. It is also easy to handle the equipment. This concept has been implemented in Unified Learning Platform kit which increases the efficiency.

Review On SOI MOSFET For Low Power Digital Application

Vol. 5  Issue 1
Year: 2014
Issue: Sep-Nov 
Title: Review On SOI MOSFET For Low Power Digital Application
Author Name: Nitu Rao, Vimal Kumar Mishra and R.K. Chauhan
Synopsis:
Several Metal Oxide Semiconductor (MOS) structures are discussed in this paper namely Silicon on Insulator (SOI) MOSFET, Partially Depleted (PD) SOI MOSFET, Fully Depleted (FD) SOI MOSFET and tunnel diode body contact MOSFET. SOI MOSFET has certain advantages over conventional bulk MOSFET in terms of reduced short channel effect and drain induced barrier lowering. But SOI MOSFET has certain problems due to its buried oxide layer. So the comparative study of different SOI MOSFET over bulk MOSFET has been taken. To overcome the problem of Floating Body Effect and high series resistance different structures of FD SOI MOSFET are explained in brief. A Tunnel Diode Body Contact SOI MOSFET is also studied in this paper to overcome the problem of Floating Body Effect in PD SOI MOSFET.

Review On Tunnel SRAM For Low Power Applications

Vol. 5  Issue 1
Year: 2014
Issue: Sep-Nov 
Title: Review On Tunnel SRAM For Low Power Applications
Author Name: Alka Parihar, Vimal Kumar Mishra and R.K. Chauhan
Synopsis:
This paper presents a brief review on different types of Tunnel Static Random Access Memory that has been proposed for low power applications. Many authors and researchers have worked on tunnel SRAM, RTD/HFET low standby power, SRAM gain, cell and Bistable Body Tunnel SRAM and demonstrated the accomplished improvements in power dissipation and performance compared with previous designs for low-power memory operation. It broadly relates to SRAM cell employing a Tunnel Switched Diode (TSD) that acts as the storage medium and is controlled by a pass transistor.

Comparative Analysis Of Integrated Wideband/Narrow Band Antenna For Cognitive Radio Applications

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Comparative Analysis Of Integrated Wideband/Narrow Band Antenna For Cognitive Radio Applications
Author Name: Srithar A and E. D. Kanmani Ruby
Synopsis:
Cognitive radio is an inventive system to wireless technologies, in which radios are designed with an astonishing level of intelligence and agility. This handles the available spectrum in an expedient manner to avoid spectrum scarcity. The cognitive radio antenna consists of integrated wideband and narrow band antenna in same substrate which is taxing task. A UWB (Ultra Wide Band) antenna is pondered for the wide band operation which has the bandwidth of 7.5GHz respectively used for sensing vacant slots in the spectrum. Narrow band antenna and pattern Reconfigurable antenna are usually used for transmission of data through the vacant slots from the outcomes of sensing antenna. In this paper, the various cognitive radio antennas are investigated in tremendously.

A Novel Based Approach For A High Speed 24 Bit Multiplier

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: A Novel Based Approach For A High Speed 24 Bit Multiplier
Author Name: Duvvuru Praveen Kumar, M.Bharathi and Mounika Tunga 
Synopsis:
Multiplication plays an important role in most mathematical applications. Among the four arithmetic operations, multiplier is the most important one. In this paper, the authors have proposed a multiplier which operates on two 24 bit of digital numbers, which is a 24 bit multiplier. In order to construct a 24 bit multiplier, the authors used Dadda reduction technique. Dadda reduction technique operates on two 24 bit numbers , hence called a 24 bit multiplier. These higher bit multipliers are used in floating point multiplications, i.e., floating point operates based on single precision and double precision numbers. In order to operate them while doing multiplication, the mantissa has 24 bits, whereas double precision requires 48 bits. This is designed using Verilog Hardware description language. This is simulated using Xilinix ISE 10.1 and being implemented on Spartran 3E of FPGA.

Design Of Electronic Circuits Using Parallel Genetic Algorithms

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Design Of Electronic Circuits Using Parallel Genetic Algorithms
Author Name: Mohammed A. Abdala and Ali Usamalcherchefchi
Synopsis:
An electronic circuit design based on Parallel Genetic Algorithm (PGA) is presented in this paper. The design uses SPICE Simulation Program with Integrated Circuit Emphasis to evaluate the circuit performance and compare it to the requirements. A Parallel Genetic Algorithm is designed and implemented on a group of desktop PCs running Windows XP nd and connected together using a standard Ethernet office network. The PGA is used in the design of several circuits, 2nd order active Low Pass Filters, a 6th order active LPF, (Low Pass Filter) and a CMOS (Complementary Metal Oxide Semiconductor) operational amplifier. The result shows the excellent extraction of circuit performance characteristics from the SPICE for different circuit types and also the importance of the algorithm increases as the complexity of the circuit increases. The parallelization achieved a speedup of about (19) times faster than a sequential implementation by using (20) processors. Further speedup is expected if more processors are used. The system is implemented using the C++ programming language.

Flip Flop Based Multilevel Inverter Topology Using Digital Control

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Flip Flop Based Multilevel Inverter Topology Using Digital Control
Author Name: C.R. Balamurugan, S.P. Natarajan, M. Arumugam and R. Bensraj 
Synopsis:
Multilevel inverter is a device which is capable of producing different voltage levels. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes.This paper proposes cascaded multilevel inverter using flip flop and logic gate. By using the four bit counter, the Boolean equation is formed from the switching table. The equations are given as the input to each switch of the multilevel inverter by using the logic gates. The proposed topologies can produce the outputs which are nearer to the sinusoidal wave. This proposed system is used to reduce the Total Harmonic Distortion (THD). A great perfection in voltage level number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter a detailed study of losses and Peak Inverse Voltage (PIV) of the proposed multilevel inverter is given.Finally a computer simulation using Matlab/Simulink is presented and a laboratory prototype implementation verifies the results.