High Resolution Display Systems Using Current-Steering DAC

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : High Resolution Display Systems Using Current-Steering DAC

Author Name : Rekha Rekha P, N. Vijayanandam N. Vijayanandam

Synopsis :

This paper focusses on foreground calibration technique. For high speed and high resolution video applications, current steering DAC is preferred. In the large current sources, linearity error is introduced and detected by using two current tunning loops and digital controller. In this paper, Vcm based switching method injected between MUX and DAC to compensate the error which reduces the time of operation. For 12-bit DAC prototype realized 90nm CMOS process,90% gate area reduction current source array is achieved. The measurement result demonstrates that the calibrated converter achieves both DNL and INL less than 1LSB.

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Accumulator Based Test Pattern Generation Of Multiple Single Input Change Vectors

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Accumulator Based Test Pattern Generation Of Multiple Single Input Change Vectors

Author Name : jayadevi S, Santhiyakumari N

Synopsis :

This paper discusses about an efficient Test Pattern Generator (TPG) for built-in self-test. This method generates Multiple Single Input Change (MSIC) vectors in a pattern.A reconfigurable Johnson counter and an accumulator is combined to generate a class of minimum transition sequences. The TPG used in this paper is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also explained to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results shows that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are used. Simulation results with ISCAS benchmarks demonstrates that MSIC can save test power and impose no more than 10% overhead for a scan design. It also achieves the target fault coverage without increasing the test length, and also saves power up to 50%.

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Simulation of QCA Based Binary to BCD Converter in Xilinx using HDLQ

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Simulation of QCA Based Binary to BCD Converter in Xilinx using HDLQ

Author Name : sasikala Govindhasamy, Maragatharaj

Synopsis :

Quantum Dot Cellular Automata (QCA) is an emerging nanotechnology in the field of Quantum electronics for the low power consumption and high speed of operational phenomenon. Such type of circuit can be used in many digital applications where CMOS circuits cannot be used due to high leakage and low switching speed. The code converters are the basic units for conversion of data to perform arithmetic operations. A new effective binary to BCD converter design using QuantumDot Cellular Automata is presented in this paper. Compared to the available code converters in VLSI technology, this method of using Quantum dots reduces area and increases switching speed. 3-input Majority gate is the basic and universal gate in QCA design. In accordance with the code converter design using 3-input majority gate logic, a 5-input majority gate logic structure is also used here to design the binary to gray code converter. This replacement improves the speed of the system by reducing number of clock cycles required to produce the output. The simulations are done using Xilinx ISE Design suite to get power and timing analysis.

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Binary Morphology With Image Compression And Cryptography

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : Binary Morphology With Image Compression And Cryptography

Author Name : Ponshankar B, Swaranambigai.R

Synopsis :

Ponshankar and his co-author Swaranambigaidesigned a Mathematical Morphology (MM) method for binary images, and extended thatfor applying to many different image representations.The stall-free low-complexity architecture has been proposed for taking advantage of the morphological duality principle and Structuring Element (SE) decomposition. The simulation results are more convenient than the mixed grain architectureand providean efficient blind binary image authentication scheme.

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Performance Comparison of Carbon Nanotube, Graphene Nano Ribon and Silicon Nanowire Transistors

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : Performance Comparison of Carbon Nanotube, Graphene Nano Ribon and Silicon Nanowire Transistors

Author Name : S. B. Siddique, T. M. Faruki , B.C. Sarkar , Md. Mahmudul Hasan

Synopsis :

Siddique et.alanalyzed the performance potential of ballistic CNT, Graphene and Silicon Nanowire(SiNW) field effect transistors for future high-performance applications. The simulation is carried out on single sub-band top of the barrier model and the common off-current value is set as 10nA.The result shows that the CNT transistor is a good amplifier and the transconductance is high compared to GNR and SiNW transistors by showing higher frequency performance and higher transconductance.

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Performance Analysis of Low-Density Parity-Check Codes for M-QAM Systems

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : Performance Analysis of Low-Density Parity-Check Codes for M-QAM Systems

Author Name : HIRALD DWARAKA PRAVEENA, C.Subhas , padmaja nimmagadda

Synopsis :

Hirald Dwaraka Praveena et.al proposed a M-QAM scheme for achieving spectral efficiency of high order modulation. For low complexity decoding, low cost and low bit-error rate LDPC (Low-Density Parity-Check) codes are chosen using encoding and decoding methods. Error Correcting Codes (ECCs) are determined for detecting and correcting errors for increasing the system throughput, speed and reducing power consumption. The simulated results are more reliable compared to Turbo codes.

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A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity

Vol.4  No.1

Year: 2013

Issue: Sep-Nov

Title : A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity

Author Name : sandhiya vijayakumar, S. Karthick , M.Valarmathy

Synopsis :

Sandhiya et.al developed CSM and PSM approaches for implementing reconfigurable higher order filters with low complexity. Greedy CSE (Common Subexpression Elimination) algorithm is applied for achieving reduction in complexity. Binary based fir filter gives 33% better reduction than CSD based CSE method. Finally, mentorgraphics tool and Xilinx(synthesis) are used to simulate and compare the results of CSD and Binary based CSE, greedy, VCSE and HCSE techniques for finding the best one adder reduction method in low complexity FIR filter.

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