Volume 9 Issue 2 December - February 2019
Research Paper
Low Power Design for Testability Implementation for Asynchronous FIFO
Madhu Kumar Patnala*, R. Nagendra**
*_** Assistant Professor (SL), Center for VLSI & Embedded Systems, Department of Electronics and Communication Engineering, SreeVidyanikethan Engineering College, (Autonomous) Tirupati, Andhra Pradesh, India.
Patnala,M.K.,Nagendra,R.(2019).Low Power Design for Testability Implementation for Asynchronous FIFO.i-manager’s Journal on Electronics Engineering,9(2),24-28. https://doi.org/10.26634/jele.9.2.15142
Abstract
A First in First out (FIFO) is used as a memory buffer between two asynchronous systems with simultaneous write and read access to and from the FIFO, where these accesses being independent of one another. Sequential operation of FIFO is particularly useful for implementing system level functions like Packet Buffering, Frequency Coupling, and Bus Matching. Asynchronous FIFO is a memory file, which uses synchronization for reading and writing with different clocks, by performing the conditions of over-run and under-run. In essence, the transfer of data from read domain to write domain with different frequencies. To generate overrun and under-run status flags, the synchronization takes place with the help of “preceding operation”of both the write and read pointers. In this design, the gray code converters are used to reduce switching activity and the low power Design for Testability (DFT) technique was applied by considering the two phases that is scan insertion and ATPG Simulations. This design is executed by using synthesizable VERILOG (Register Transfer Level) RTL Code and verified with Xilinx ISE simulator.
