A Study on Globally Asynchronous and locally Synchronous System

Volume 8 Issue 3 March - May 2018

Research Paper

A Study on Globally Asynchronous and locally Synchronous System

Appaneni Srija Chowdary *, M.Bharathi**

* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, Andhra Pradesh, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, Andhra Pradesh, India.

Chowdary. A. S and Bharathi. M (2018). A Study on Globally Asynchronous and locally synchronous System. i-manager's Journal on Electronics Engineering, 8(3), 26-31. https://doi.org/10.26634/jele.8.3.14416

Abstract

Due to declining technologies and increasing design extent, it is becoming high-priced and troublesome to allocate a global clock signal all through the chip. To overcome this, asynchronous processor design is considered as they do not have global clock. In contrary processor industry makes over a change from synchronous to asynchronous logic. Power and robustness differ notably from synchronous to asynchronous circuits. Synchronous blocks which are communicated by asynchronous links in SoC design is a challenging task. Hence, Globally Asynchronous Locally Synchronous (GALS) system is an appropriate technique, as they merge the advantages of both the Synchronous and Asynchronous approaches. International Technology Roadmap for Semiconductors (ITRS) have detailed that the usage of asynchronous logic doubles by 2024. Asynchronous logic resolves the difficulties that occur in synchronization. Fully Synchronous and GALS are two design approaches to detect a signal in the module of the signal processing system. The primary objective is to demonstrate a low power implementation of GALS system.

The system reduces the large Electro Magnetic Interface (EMI) when an active clock is generating large spikes at the supply current in the synchronous circuit. In order to avoid failures of the synchronous circuits, asynchronous wrappers are used for communication in between the synchronous blocks, where the stability of such systems are to be verified. By using asynchronous wrapper in a synchronous island, one can meet the full design requirements and a single die requires large number of clock frequencies because various IP cores are integrated on a complex systems. An efficient technique to design these kind of distributed SoC is GALS. Some clocking schemes are used here to investigate a number of independent clocks on synchronous domains and to obtain reliable transfer of data and low latency. The efficient systems with hardware complexity, global clock rate reduction, and low power consumption use this kind of technique.

Sensitivity Analysis By Active Layer And Dielectric Scaling Of An Organic Thin Field Effect Transistor Based Sensor

Volume 8 Issue 3 March - May 2018

Research Paper

Sensitivity Analysis By Active Layer And Dielectric Scaling Of An Organic Thin Field Effect Transistor Based Sensor

Harshita Pathak*, Himanshu Shukla**

* PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh,India.

** PG Scholar, Department of Electrical Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India.

Pathak. H and Shukla. H (2018). Sensitivity Analysis by Active Layer and Dielectric Scaling of an Organic Thin Field Effect Transistor based Sensor. i-manager's Journal on Electronics Engineering, 8(3), 18-25. https://doi.org/10.26634/jele.8.3.14388

Abstract

A low cost highly sensitive organic thin film transistor based organic gas sensor has been investigated with pentacene as an active and sensing layer. The variation in work function of source is lured due to gas adsorption, minimised carrier mobility, and soaring source and also drain resistance has paved way for a change in minimum and maximum drain current. On varying the width of active layer along with dielectric, significant variation was observed in turn on current, and minimum and maximum drain current over a constant threshold voltage on different source to drain width architecture. Consequently, sensitivity was formulated along with average sensitivity. The organic thin film transistor planted devices have emerged to be superior class of sensors.

A Novel Diode Free Adiabatic Logic Threshold Inverter Quantizer for Flash ADC

Volume 8 Issue 3 March - May 2018

Research Paper

A Novel Diode Free Adiabatic Logic Threshold Inverter Quantizer for Flash ADC

Vishal Moyal*, Neeta Tripathi**

* Associate Professor, Department of Electronics and Telecommunication Engineering, SSTC, Bhilai, Chhattisgarh, India.

** Principal, Shri Shankaracharya College of Engineering, SSTC, Bhilai, Chhattisgarh, India.

Moyal. V and Tripathi. N (2018). A Novel Diode Free Adiabatic Logic Threshold Inverter Quantizer for Flash ADC. i-manager's Journal on Electronics Engineering, 8(3), 14-17. https://doi.org/10.26634/jele.8.3.14386

Abstract

A novel Diode Free Adiabatic Logic (DFAL) based Threshold Inverter Quantizer (TIQ) is suggested in this work for implementing a 3-bit Flash type Analog to Digital Converter (FADC). For appropriate implementation of such TIQ, there is a necessity of rehabilitated reference voltage for each of the comparator and this task is accomplished methodically by sizing the transistors of the TIQ comparators. The suggested work is carried out with TSMC 65 nm Technology on Cadence- Virtuoso-IC616 version. The average power dissipation by the proposed FADC simulated at 1.2 V and for 1fF capacitive load is 5.5 μW, which is 66 % less than that of the power consumed by CMOS-TIQ based FADC at 100 Hz.

Monitoring and Control of Gas Leakages of Industrial Sector Using PIC 18F4550, ZigBee and Wireless Sensor Actuator Network

Volume 8 Issue 3 March - May 2018

Research Paper

Monitoring and Control of Gas Leakages of Industrial Sector Using PIC 18F4550, ZigBee and Wireless Sensor Actuator Network

Prashant V. Mane-Deshmukh*, D. M. Adat**, B. P. Ladgaonakar***, S. K. Tilekar****

* Assistant Professor, Department of Electronics Engineering, Shankarrao Mohite Mahavidyalaya, Akluj.

**,**** Associate Professor, Department of Electronics Engineering, Shankarrao Mohite Mahavidyalaya, Akluj.

*** Head, Post Graduate Department of Electronics Engineering, Shankarrao Mohite Mahavidyalaya, Akluj.

Deshmukh. P. V. M., Adat. D. M., Ladgaonakar. B. P. and Tilekar S. K. (2018). Monitoring and Control of Gas Leakages of Industrial Sector Using PIC 18F4550, Zigbee and Wireless Sensor Actuator Network. i-manager's Journal on Electronics Engineering, 8(3), 5-13. https://doi.org/10.26634/jele.8.3.14387

Abstract

Nowadays, Atomization is the need of an industrial sector for processing various sections of a typical industry. On survey it is observed that Atomization may help to increase the reliability, quality, security and reduce cost. The Wireless Sensor Actuator Network (WSAN) is the challenging technology in the field of Industrial sectors, has been proposed in this paper to monitor, detect, and control the leakage of gases. The present research work is carried out to detect and control the hazardous gas in industrial transportation system to avoid the catastrophic accidents as well as reduce effect on environment. For this purpose, Sensor Actuator Node (SA-Node) is wired about PIC 18F4550 microcontroller along with sensing and signal conditioning capabilities. The IEEE 802.15.4 standard is deployed for wireless communication. On the other hand, the control action is carried out through Coordinator SA-Node, which is capable for the electromechanical action. To synchronize the on-chip as well as off-chip peripherals, the firmware is developed realizing the concept of real time operating system. It is observed that the system works satisfactorily with great accuracy.

A Compact Tunable Floating Gate MOSFET based Resistor

Volume 8 Issue 3 March - May 2018

Research Paper

A Compact Tunable Floating Gate MOSFET based Resistor

Dinesh Prasad*, Charu Rana**, Neelofer Afzal***

*Associate Professor, Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi, India.

**Research Scholar, Jamia Millia Islamia, New Delhi, India.

Assistant Professor, Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi, India.

Prasad. D., Rana. C and Afzal. N (2018). A Compact Tunable Floating Gate MOSFET based Resistor. i-manager's Journal on Electronics Engineering, 8(3), 1-4. https://doi.org/10.26634/jele.8.3.14385

Abstract

A simple tunable grounded voltage controlled floating gate metal oxide semiconductor field effect transistor based resistor is proposed in this paper. Highly linear resistance is obtained by cancelling the non-linear term present in the drain current of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with the help of Floating Gate Metal Oxide Semiconductor Field Effect Transistors (FGMOSFETs). The attenuation function is performed by two FGMOSFETs and this signal is fed to the gate terminal of N- channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET). The input current is applied on the drain terminal of the N- channel Metal Oxide Semiconductor Field Effect Transistor. The drain current equation of the metal Oxide Semiconductor Field Effect Transistor is utilized to achieve the equivalent linear resistance. The features exhibited by a resistor are simplicity, smaller area, broad range of programmability, and wider bandwidth. The range of the resistance observed is from 3.6 kΩ to 10.58 kΩ for the varied control voltage from 1.5 V to 2.4 V. The frequency response of the proposed resistor measured is 288 MHz. The total power dissipation obtained is 22.5 μW. The circuit is verified by simulation after applying macro model of the FGMOSFET. The circuit is simulated using SPICE on 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology to demonstrate the efficacy of the proposed circuits. The presented circuit is beneficial for analog signal processing applications that functions in low power.

Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET

Volume 8 Issue 2 December - February 2018

Research Paper

Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET

Manvendra Chauhan*, Rajeev Kumar Chauhan**

PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India.

Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India

Chauhan. M. S and Chauhan. R. K (2018). Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET. i-manager's Journal on Electronics Engineering, 8(2), 44-50. https://doi.org/10.26634/jele.8.2.14140

Abstract

In this paper, the authors have presented a junctionless Fully Depleted Silicon on Insulator (FDSOI) Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) with a source engineering on an intrinsic silicon body, with the purpose to improve I /I ratio of a transistor at low thermal budget process. The proposed device consists of a very ON OFF small region of high doping, over dopingless region of the source. The charge plasma concept is also employed to introduce charge plasma on the source and drain region, by using metal electrodes of appropriate work function. In this way, dopingless region of the source and drain gets electrostatically induced, whereas charge carrier density rises in an already doped region of the source. This makes the proposed device to combine the benefits of modified source fully depleted silicon-on-insulator MOSFET (MS FDSOI MOSFET) (i.e., high I current and I /I ratio) and conventional ON ON OFF junctionless transistors plus the transistors with intrinsic Source/Drain (S/D) regions (i.e., low thermal budget process). The electrical properties of the proposed device are simulated and compared with that of conventional MS FDSOI MOSFET.

DC Analysis of Silicon Plated Germanium Pin Diode

Volume 8 Issue 2 December - February 2018

Research Paper

DC Analysis of Silicon Plated Germanium Pin Diode

Shivangi Sonkar*, R.K. Chauhan**

PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India.

Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India.

Sonkar. S and Chauhan. R.K (2018). DC Analysis of Silicon Plated Germanium Pin Diode. i-manager's Journal on Electronics Engineering, 8(2), 39-43. https://doi.org/10.26634/jele.8.2.14139

Abstract

In this paper, a parametric study of silicon based PIN diode and Silicon Plated Germanium (SPG) PIN diode is performed th and comparative study is presented. SPG is a germanium diode containing 1/10 width of N+ region doped with silicon. The comparative study is performed on different parameters such as P+ layer and N+ layer concentration, Intrinsic layer thickness, P+ region and N+ region width, and Intrinsic region width. The results obtained from simulation shows that the forward current conduction of SPG PIN diode is greater than silicon device and hence, the resistance offered by SPG is far less than silicon device . The whole work of this paper is done with the help of SILVACO simulator tool.