OTRA Based Precision Rectifier

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: OTRA Based Precision Rectifier
Author Name:Rashika Anurag, Neeta Pandey, Rajeshwari Pandey, and Ritu Vijay
Synopsis:

Analog integrated circuit design is receiving a tremendous boost due to the development and application of Current- Mode (CM) processing. Application of CM techniques provides wider bandwidth; which is virtually independent of the closed loop gain, greater linearity and large dynamic range. The Operational Transresistance Amplifier (OTRA) has emerged as an effective alternate current mode analog building block. It is a high gain current input, voltage output amplifier and also free from parasitic input capacitances and resistances as its input terminals are virtually grounded thus eliminating response limitations due to parasitics. OTRA is used as an analog building block for realizing a number of circuits having applications in signal processing and generation. Precise rectification is an important requirement in instrumentation and measurement circuits and is addressed in this paper. Traditionally, diodes are used to build rectifiers however; rectification is not permitted below a voltage of ∼ 0.7 V for silicon and ∼ 0.3 V for germanium diodes due to cutin voltage. For low voltage applications, Operational Amplifiers (OPAMP) with diode connected in feedback is used which prevents the fast switching of the diodes in high frequency range due to slew rate limitation of OPAMP. This paper aims at presenting an OTRA based FWR which is suitable for low voltage rectification. The functionality of the proposed circuit is validated through SPICE simulation for which OTRA is realized using Current Feedback Operational Amplifier (CFOA).The simulation results are found in close agreement to the theoretical results.

Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop
Author Name:S. Suvarna, K. Rajesh, and S. Veerakumar
Synopsis:

Digital multipliers are most efficiently used in many applications such as Fourier Transform, Discrete Cosine Transforms, and Digital Filtering for high speed and low power consumption. The throughput of the multipliers is based on speed of the multiplier, and if it is too slow then, the entire performance of the circuit will be diminished. The pMOS transistor in negative bias cause Negative Bias Temperature Instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause Positive Bias Temperature Instability (PBTI). These effects reduce the transistor speed and the system may fail due to timing violations. So here, a new multiplier was designed with novel Adaptive Hold Logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), it is possible to reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

Trichotomous Bayes Factor Analysis [Tri–BFA]: A Post Hoc Probability Confirmatory Data Analysis Assurance Model Designed to Determine the Validity, Viability, and Verifiability of E–Learning Hypotheses

Vol. 6  Issue 1
Year: 2015
Issue:Sep-Nov
Title: Trichotomous Bayes Factor Analysis [Tri–BFA]: A Post Hoc Probability Confirmatory Data Analysis Assurance Model Designed to Determine the Validity, Viability, and Verifiability of E–Learning Hypotheses
Author Name:James Edward Osler
Synopsis:

This paper presents meticulous knowledge about ‘Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content for Electronics and Digital Learning Ecosystems’. This narrative provides an epistemological rational for the use of Bayesian probability statistical testing models for E–Learning via the Tri–Squared Test and subsequent TRINOVA Post Hoc test methodology. TRINOVA is an in–depth [Trichotomous Nomographical Variance] statistical procedure for the internal testing of the transformative process of qualitative data into quantitative outcomes through the Tri–Squared Test. Tri–Bayes Factor Analysis (or “Tri–BFA”) is an advanced statistical measure that is designed to check the validity and reliability of a Tri–Squared Test hypothesis using Bayesian probability. This is a novel approach to advanced statistical post hoc Tri–Squared hypothesis testing. It adds merit and considerable value to the mixed methods approach of research design that involves the holistic combination and comparison of qualitative and quantitative data outcomes. A sequential series of steps using the Tri–Squared Test, TRINOVA, and Tri–BFA mathematical models are provided to illustrate the entire process of advanced statistical Trichotomous inquiry.

Simulation Analysis and Design of an Optimized Controller Model for Photovoltaic System Under Uniform and Non-Uniform Shaded Conditions

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Simulation Analysis and Design of an Optimized Controller Model for Photovoltaic System Under Uniform and Non-Uniform Shaded Conditions
Author Name:Kakarla Deepti, P. Srihari and K. Manjunathachari
Synopsis:

The manufacturing and utilization of photovoltaic arrays have advanced dramatically in the recent years. The use of new, efficient Photovoltaic Solar Cells (PVSCs) has emerged as an alternative measure of renewable green power, energy conservation and demand side management. Maximum Power Point Tracking (MPPT) techniques are employed in photovoltaic (PV) systems to make full utilization of PV array output which depends on solar irradiation and temperature. These techniques vary in many aspects as range of effectiveness, hardware, sensor required and cost. This paper presents an optimized controller design which increases the conversion efficiency of a photovoltaic system under variable temperature and irradiance conditions. It also includes the comparison of the efficiency of the PV system by incorporating the controller circuit on the existing MPPT algorithms in real time and in simulation. Different development stages are presented and then the optimized controller is simulated and evaluated which has shown better performances. Matlab Simulink tools have been used for performance evaluation on energy point. Simulation will consider different solar irradiance and temperature variations. The real time model produced includes rotating the panel under uniform and non uniform shaded conditions which is driven by a brush motor.

Voltage Mode Universal First Order Filter Employing Single OTRA

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Voltage Mode Universal First Order Filter Employing Single OTRA
Author Name:Honey Gahlawat, Hemant Kumar, Jatin Kamnani, Gaurav Dagar and Rajeshwari Pandey 
Synopsis:

Mixed mode circuit design is the current trend in VLSI industry, where both analog and digital circuitry can be fabricated using standard digital CMOS technologies. However, these technologies do not lend themselves to analog design, requirting novel circuit design techniques that are compatible with standard CMOS processes. Consequently, over the last few decades Current-Mode (CM) processing has evolved as a novel design technique which has resulted in emergence of numerous analog building blocks. The operational transresistance amplifier (OTRA) is one among those. It is a high gain current input voltage output device which provides the advantages of current mode design techniques and can readily be used for voltage-mode applications.

This paper presents a new voltage mode Multi-Input Single Output (MISO) first order universal filter using single OTRA. The presented topology can be used to realize low-pass, high-pass and all-pass filter functions through appropriate input selections. The configuration is made fully integrated by implementing the resistors using matched transistors thereby reducing chip area. The proposed circuit is insensitive to parasitic capacitances and resistances due to internally grounded input terminals of OTRA. The effect of non-ideality of OTRA on the proposed circuit is also analysed. Functionality of the proposed configuration is verified through PSPICE simulations using 0.5 μm CMOS process parameters. The simulation results are in tune with the theoretical propositions.

Study of HEMTs Thermal Parameters Based on I-V Characteristics Analysis

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Study of HEMTs Thermal Parameters Based on I-V Characteristics Analysis
Author Name:Leonardo Suriano, Roberto Marani and Anna Gina Perri
Synopsis:
This paper presents a light DC thermal model of recessed gate P-HEMT devices, based on the Chaibi model, where the authors have identified the transistor parameters having greater influence on the device behaviour for temperature variations. The main aims are to improve the accuracy of modelled I-V curves, in particular in the knee and saturation regions and above all to give the device source-drain current as a function of external voltages, as seen at the device gates, by-passing the very difficult measurement of parasitic resistances for the I-V characterisation. To verify the accuracy of the proposed model, the results are compared with those of Chaibi model, obtaining a negligible relative error, with however a compilation time and a run time much more low.

Introducing Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content For Electronics and Digital Learning Ecosystems

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Introducing Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content For Electronics and Digital Learning Ecosystems
Author Name:James Edward Osler II 
Synopsis:
This monograph provides an epistemological rational for the novel “Tri–Factor Analysis” statistical model and metric. This new statistic is an innovative and in–depth way of investigating the overall effectiveness of teaching and learning in digital learning environments and Ecosystems. Tri–Factor Analysis is grounded in the Eduscience (Osler, 2013a) Tri–Factors of: Performance, Efficacy, and Content. Along with the Tri–Squared Test (first introduced in the Journal on Mathematics) it is a mathematically–grounded analytical methodology designed to provide educators with quantitative tools, metrics, and analytics that aid in pedagogical (and andragogical) investigation. The use of the Tri–Factor Analysis methodology also adds value to educational inquiry that has been formatted as an eduscientifically–engineered research design that involves the critical analysis of overall classroom and individual learning in digital learning Ecosystems.