Voltage Mode Universal First Order Filter Employing Single OTRA

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Voltage Mode Universal First Order Filter Employing Single OTRA
Author Name:Honey Gahlawat, Hemant Kumar, Jatin Kamnani, Gaurav Dagar and Rajeshwari Pandey 
Synopsis:

Mixed mode circuit design is the current trend in VLSI industry, where both analog and digital circuitry can be fabricated using standard digital CMOS technologies. However, these technologies do not lend themselves to analog design, requirting novel circuit design techniques that are compatible with standard CMOS processes. Consequently, over the last few decades Current-Mode (CM) processing has evolved as a novel design technique which has resulted in emergence of numerous analog building blocks. The operational transresistance amplifier (OTRA) is one among those. It is a high gain current input voltage output device which provides the advantages of current mode design techniques and can readily be used for voltage-mode applications.

This paper presents a new voltage mode Multi-Input Single Output (MISO) first order universal filter using single OTRA. The presented topology can be used to realize low-pass, high-pass and all-pass filter functions through appropriate input selections. The configuration is made fully integrated by implementing the resistors using matched transistors thereby reducing chip area. The proposed circuit is insensitive to parasitic capacitances and resistances due to internally grounded input terminals of OTRA. The effect of non-ideality of OTRA on the proposed circuit is also analysed. Functionality of the proposed configuration is verified through PSPICE simulations using 0.5 μm CMOS process parameters. The simulation results are in tune with the theoretical propositions.

Study of HEMTs Thermal Parameters Based on I-V Characteristics Analysis

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Study of HEMTs Thermal Parameters Based on I-V Characteristics Analysis
Author Name:Leonardo Suriano, Roberto Marani and Anna Gina Perri
Synopsis:
This paper presents a light DC thermal model of recessed gate P-HEMT devices, based on the Chaibi model, where the authors have identified the transistor parameters having greater influence on the device behaviour for temperature variations. The main aims are to improve the accuracy of modelled I-V curves, in particular in the knee and saturation regions and above all to give the device source-drain current as a function of external voltages, as seen at the device gates, by-passing the very difficult measurement of parasitic resistances for the I-V characterisation. To verify the accuracy of the proposed model, the results are compared with those of Chaibi model, obtaining a negligible relative error, with however a compilation time and a run time much more low.

Introducing Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content For Electronics and Digital Learning Ecosystems

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: Introducing Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content For Electronics and Digital Learning Ecosystems
Author Name:James Edward Osler II 
Synopsis:
This monograph provides an epistemological rational for the novel “Tri–Factor Analysis” statistical model and metric. This new statistic is an innovative and in–depth way of investigating the overall effectiveness of teaching and learning in digital learning environments and Ecosystems. Tri–Factor Analysis is grounded in the Eduscience (Osler, 2013a) Tri–Factors of: Performance, Efficacy, and Content. Along with the Tri–Squared Test (first introduced in the Journal on Mathematics) it is a mathematically–grounded analytical methodology designed to provide educators with quantitative tools, metrics, and analytics that aid in pedagogical (and andragogical) investigation. The use of the Tri–Factor Analysis methodology also adds value to educational inquiry that has been formatted as an eduscientifically–engineered research design that involves the critical analysis of overall classroom and individual learning in digital learning Ecosystems.

A Review on Miniaturized Microstrip Technology along with Metamaterial for Low Pass filter application

Vol. 5  Issue 4
Year: 2015
Issue: Jun-Aug
Title: A Review on Miniaturized Microstrip Technology along with Metamaterial for Low Pass filter application
Author Name: Akshay Kumar Srivastava, Arvind Pandey and B.S.Rai 
Synopsis:
This paper provides knowledge about how to decrease the overall physical size and insertion loss of the filter. Metamaterial is taken as a reference to achieve this goal. Physical size and light weight is a major concern in today's integrated circuit. The application of low pass filter is very wide in the field of communication engineering and the complex receiver in which frequency selection is a primary factor and much more. The rate of change of magnitude with respect to frequency (roll off) and the magnitude in pass band are two most important features of any filters. The particular shape of metamaterial having various unit cell has ability to improve the overall performance of filter. This improves selectivity to great extent. Metamaterial in shape of hexagonal-omega structure provides the negative permittivity.

A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application
Author Name: Nitu Rao, Vimal Kumar Mishra and R.K. Chauhan
Synopsis:
In this paper Tunnel Diode Body Contact (TDBC) SOI p-MOSFET with low off-state leakage current is proposed for low power -13 digital application. The device shows off-state current with a drain voltage of 0.5V as about equal to 3.37×10 A -4 9 (33.7pA) and on-state current as about equal to 1.5×10 A (0.15mA) so that on to off-state current ratio is about 10 . This paper also includes the study of different type of SOI MOSFET namely Partially Depleted SOI (PD SOI), Full Depleted SOI (FD SOI) for low power digital application. This paper also includes the comparison between Partially Depleted TDBCS SOI n- MOSFET and proposed TDBC SOI p-MOSFET.

A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles
Author Name: Mareddi Bharathkumar, Palagani Yellappa and D. Revanth 
Synopsis:
In this paper, a novel pliant nanogenerator made of PDMS (polydimethylsiloxane) and ZnO nanoparticles is presented. In this device, ZnO nanoparticles are combined with PDMS to form a nanogenerator. PDMS is a flexible kind of material, which is used to form flexible kind of materials and ZnO is a piezoelectric material which exhibits piezoelectricity. A nanogenerator converts mechanical energy into electrical energy. Mechanical energy refers to energy that we are getting from the surroundings like mechanical pressure, mechanical vibrations, etc. By using this energy we can charge batteries of mobile phones and operate smaller electronic devices through wireless power transmission and also it can give endless power in wireless sensor applications. Now a days people are mainly facing problems with power and low battery power. So, to avoid these problems, energy harvesting is playing a main role in industries. Our work indicates the realization of plaint nanogenerator made of ZnO nanoparticles and PDMS and it has some important and interesting applications in energy harvesting. The applications are mainly for low power electronic devices.

An Efficient Design Of XOR Gate And Its Applications Using QCA

Vol. 5  Issue 3
Year: 2015
Issue: Mar-May
Title: An Efficient Design Of XOR Gate And Its Applications Using QCA
Author Name: D. Ajitha , K. Venkata Ramanaiah and V. Sumalatha
Synopsis:
As a substitute for CMOS, innovation of quantum cellular automata was anticipated by Lent et al, to represent exemplary cell automata with quantum dots. Quantum Cellular Automata (QCA) may be a progressive innovation that endeavors the certain nano level issues to perform computing. Its potential advantages are high speed, high device density, and low power dissipation. This paper presents the design of XOR gate with the least number of cells; furthermore the circuit appearance is simple. Exploitation of this novel XOR gate leads to the development of combinational circuits like Half Adder, Full Adder, Parity Generator and Parity Checker etc., which were developed effectively in a single layer structure with less number of cells, area and delay, as compared to the earlier designs. This paper mainly focusses on the construction of optimized combinational circuits without using cross-overs in QCA. Further, the simulation results are presented.