Review On Tunnel SRAM For Low Power Applications

Vol. 5  Issue 1
Year: 2014
Issue: Sep-Nov 
Title: Review On Tunnel SRAM For Low Power Applications
Author Name: Alka Parihar, Vimal Kumar Mishra and R.K. Chauhan
Synopsis:
This paper presents a brief review on different types of Tunnel Static Random Access Memory that has been proposed for low power applications. Many authors and researchers have worked on tunnel SRAM, RTD/HFET low standby power, SRAM gain, cell and Bistable Body Tunnel SRAM and demonstrated the accomplished improvements in power dissipation and performance compared with previous designs for low-power memory operation. It broadly relates to SRAM cell employing a Tunnel Switched Diode (TSD) that acts as the storage medium and is controlled by a pass transistor.

Comparative Analysis Of Integrated Wideband/Narrow Band Antenna For Cognitive Radio Applications

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Comparative Analysis Of Integrated Wideband/Narrow Band Antenna For Cognitive Radio Applications
Author Name: Srithar A and E. D. Kanmani Ruby
Synopsis:
Cognitive radio is an inventive system to wireless technologies, in which radios are designed with an astonishing level of intelligence and agility. This handles the available spectrum in an expedient manner to avoid spectrum scarcity. The cognitive radio antenna consists of integrated wideband and narrow band antenna in same substrate which is taxing task. A UWB (Ultra Wide Band) antenna is pondered for the wide band operation which has the bandwidth of 7.5GHz respectively used for sensing vacant slots in the spectrum. Narrow band antenna and pattern Reconfigurable antenna are usually used for transmission of data through the vacant slots from the outcomes of sensing antenna. In this paper, the various cognitive radio antennas are investigated in tremendously.

A Novel Based Approach For A High Speed 24 Bit Multiplier

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: A Novel Based Approach For A High Speed 24 Bit Multiplier
Author Name: Duvvuru Praveen Kumar, M.Bharathi and Mounika Tunga 
Synopsis:
Multiplication plays an important role in most mathematical applications. Among the four arithmetic operations, multiplier is the most important one. In this paper, the authors have proposed a multiplier which operates on two 24 bit of digital numbers, which is a 24 bit multiplier. In order to construct a 24 bit multiplier, the authors used Dadda reduction technique. Dadda reduction technique operates on two 24 bit numbers , hence called a 24 bit multiplier. These higher bit multipliers are used in floating point multiplications, i.e., floating point operates based on single precision and double precision numbers. In order to operate them while doing multiplication, the mantissa has 24 bits, whereas double precision requires 48 bits. This is designed using Verilog Hardware description language. This is simulated using Xilinix ISE 10.1 and being implemented on Spartran 3E of FPGA.

Design Of Electronic Circuits Using Parallel Genetic Algorithms

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Design Of Electronic Circuits Using Parallel Genetic Algorithms
Author Name: Mohammed A. Abdala and Ali Usamalcherchefchi
Synopsis:
An electronic circuit design based on Parallel Genetic Algorithm (PGA) is presented in this paper. The design uses SPICE Simulation Program with Integrated Circuit Emphasis to evaluate the circuit performance and compare it to the requirements. A Parallel Genetic Algorithm is designed and implemented on a group of desktop PCs running Windows XP nd and connected together using a standard Ethernet office network. The PGA is used in the design of several circuits, 2nd order active Low Pass Filters, a 6th order active LPF, (Low Pass Filter) and a CMOS (Complementary Metal Oxide Semiconductor) operational amplifier. The result shows the excellent extraction of circuit performance characteristics from the SPICE for different circuit types and also the importance of the algorithm increases as the complexity of the circuit increases. The parallelization achieved a speedup of about (19) times faster than a sequential implementation by using (20) processors. Further speedup is expected if more processors are used. The system is implemented using the C++ programming language.

Flip Flop Based Multilevel Inverter Topology Using Digital Control

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Flip Flop Based Multilevel Inverter Topology Using Digital Control
Author Name: C.R. Balamurugan, S.P. Natarajan, M. Arumugam and R. Bensraj 
Synopsis:
Multilevel inverter is a device which is capable of producing different voltage levels. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes.This paper proposes cascaded multilevel inverter using flip flop and logic gate. By using the four bit counter, the Boolean equation is formed from the switching table. The equations are given as the input to each switch of the multilevel inverter by using the logic gates. The proposed topologies can produce the outputs which are nearer to the sinusoidal wave. This proposed system is used to reduce the Total Harmonic Distortion (THD). A great perfection in voltage level number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter a detailed study of losses and Peak Inverse Voltage (PIV) of the proposed multilevel inverter is given.Finally a computer simulation using Matlab/Simulink is presented and a laboratory prototype implementation verifies the results.

Improvement In Noise Figure Using CMOS Broadband Sub-Threshold Mixer

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: Improvement In Noise Figure Using CMOS Broadband Sub-Threshold Mixer
Author Name: Nimain Charan Nayak
Synopsis:
This paper presents a broadband low noise mixer based on a double balanced Gilbert cell that works between 1-6 GHz. One of the most important factors of the mixer noise figure is flicker noise. All transistors in this design are biased in the subthreshold region in order to suppress mixer noise figure. Also dynamic current injection circuit (current bleeding circuit) has been utilized to improve the noise performance. Shunt peaking technique is adopted to have a flat conversion gain. The simulation results of the designed mixer show 21.1 dB conversion gain and 6.41 dB average noise figure at 1 GHz - 6 GHz. Also simulation results demonstrate that, using current bleeding circuit, low noise figure is obtained . Its consumption power is 10.6 mW at 1.8V supply voltage. The noise figure is an important parameter to be considered in the design of Gilbert cell mixer and is further improved using the proposed method. A dynamic current injection technique with a tuning inductor has been employed in the mixer design in order to reduce the output noise corner frequency. The traditional Gilbert based wideband active mixers realized by pure bipolar and MOSFET have been demonstrated in recent years.

I/O Average And Maximum Current Consumption Calculation

Vol. 4  Issue 4
Year: 2014
Issue: Jun-Aug
Title: I/O Average And Maximum Current Consumption Calculation
Author Name: Andrey Malkov, Lin Wang and Evgeny Shevchenko
Synopsis:
Power Integrity (PI) is becoming increasingly important in today's high-speed digital I/O interfaces. Power integrity for I/O interfaces is related to the voltage variations in the power/ground network due to the noise. The power/ground noise causes various problems in high-speed systems, such as logic failure, EMI, timing delay, and jitter. For the Power Integrity analysis of the I/O padring of the chip, it is very important to quickly calculate I/O current consumption at the early stage of the project, without running extensive time-consuming spice simulations of entire I/O bank. PI analysis needs both I/O padring and PCBdata, and simulation tool considers them simultaneously [5],[6],[7],[10]. Two useful formulas are given in this article and explained below that can easily allow to estimate average and maximum IO current consumption, using example of i.MX6 series applications processors of Freescale Semiconductor, Inc. Resulting numbers correlate well with real I/O circuit spice simulation data.