A Modified Partial Product Generator for Binary Multipliers using Different Adders

Vol. 6  Issue 3
Year: 2016
Issue:Mar-May
Title:A Modified Partial Product Generator for Binary Multipliers using Different Adders
Author Name:A. Divya Teja, K. Charan Kumar and K. Neelima 
Synopsis:

Digital multipliers are widely used in the arithmetic units of microprocessors, multimedia and digital signal processors. The main aim of this research work is to design high performance multipliers using different radix to different adders. Modified booth encoding technique is used in this proposed design, where extra partial products are reduced to half. Therefore, the accumulation stages are reduced. By this design, it significantly improves speed, area and delay which is a main objective and purpose of the study. Modified booth encoding technique improves the power delay product by using different types of adders with different radix such as radix-4, radix-8, and radix-16. The used adders are ripple carry adder and carry look-ahead adder, where these are used to know the exact difference by their comparison in terms of delay and area by using Xilinx ISE 14.5 tool with high performance parameters.