Modified Divide by 2/3 Counter Design Using MTCMOS Techniques

Vol.4  No.2

Year: 2014

Issue: Dec-Feb

Title : Modified Divide by 2/3 Counter Design Using MTCMOS Techniques

Author Name : Tamilmani R, Rajesh.K , Santhiyakumari N

Synopsis :

In this paper, the leakage power and speed performances of extended-true single phase clock and MTCMOS using true single phase clock prescaler are investigated. Based upon this study, MTCMOS technique is implemented in true single phase clock logic DFF design. By using a wired OR logic, only one transistor is used for both mode selection and counting logic system. The working frequency of the counter is enhanced and reduced the critical path between the DFF. Using MTCMOS technique a static leakage power is reduced and the speed performances are improved. The designed counter is compared in term of power consumption using DSCH and Micro wind tools.

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