Efficient Implementation Of Gate Oxide With And Without Breakdown In SRAM – BISR For Word Oriented Memories

Vol.4  No.3

Year: 2014

Issue: Mar-May

Title : Efficient Implementation Of Gate Oxide With And Without Breakdown In SRAM – BISR For Word Oriented Memories

Author Name : Devi priya, S.LAVANYA , ASWIN TILAK.A

Synopsis :

Scaling of the CMOS [Complementary Metal Oxide Semiconductor] technology associated with gate oxide thickness has become a major barrier for the design of circuit in nanoscale Static Random Access Memory (SRAM), especially in lower voltages. The operation of SRAM arrays are critical in reducing the power consumption. The Gate Oxide Breakdown caused by excessive electric field in the gate oxide causes increased vulnerability of the circuit performance, during breakdown. The devices are characterized by increased minimum voltage due to increase the static write failure as the voltage decreases. The design circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Micro wind 2 VLSI layout CAD tool. The proposed structures are simulated using Xilinx ISE design suite.

For more details:

imanagerpublications.com